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    Light Emitting Device
    2.
    发明申请
    Light Emitting Device 有权
    发光装置

    公开(公告)号：US20100308347A1

    公开(公告)日：2010-12-09

    申请号：US12794843

    申请日：2010-06-07

    Applicant: Wen-Yung Yeh ,  Hsi-Hsuan Yen ,  Tse-Peng Chen

    Inventor： Wen-Yung Yeh ,  Hsi-Hsuan Yen ,  Tse-Peng Chen

    IPC: H01L33/00

    CPC classification number: H01L27/156 ,  H01L23/60 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/24 ,  H01L2924/12032 ,  H01L2924/19105 ,  H01L2924/00

    Abstract: A light emitting device includes a plurality of micro diodes, which are electrically connected to constitute a bridge rectifier circuit. Each branch of the bridge rectifier circuit includes a single micro diode or a plurality of micro diodes. The light emitting device is electrically connected to an AC power source, which alternately drives the light emitting device in two current loops. Therefore, the micro diodes in two current loops of the bridge rectifier circuit emit light by turns.

    Abstract translation: 发光器件包括多个微型二极管，其被电连接以构成桥式整流器电路。 桥式整流电路的每个支路包括单个微型二极管或多个微型二极管。 发光器件电连接到AC电源，AC电源在两个电流回路中交替地驱动发光器件。 因此，桥式整流电路的两个电流回路中的微型二极管轮流发光。

    Light emitting device
    3.
    发明授权
    Light emitting device 有权
    发光装置

    公开(公告)号：US08338837B2

    公开(公告)日：2012-12-25

    申请号：US12794843

    申请日：2010-06-07

    Applicant: Wen-Yung Yeh ,  Hsi-Hsuan Yen ,  Tse-Peng Chen

    Inventor： Wen-Yung Yeh ,  Hsi-Hsuan Yen ,  Tse-Peng Chen

    IPC: H01L33/00

    CPC classification number: H01L27/156 ,  H01L23/60 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/24 ,  H01L2924/12032 ,  H01L2924/19105 ,  H01L2924/00

    Abstract: A light emitting device includes a plurality of micro diodes, which are electrically connected to constitute a bridge rectifier circuit. Each branch of the bridge rectifier circuit includes a single micro diode or a plurality of micro diodes. The light emitting device is electrically connected to an AC power source, which alternately drives the light emitting device in two current loops. Therefore, the micro diodes in two current loops of the bridge rectifier circuit emit light by turns.

    Abstract translation: 发光器件包括多个微型二极管，其被电连接以构成桥式整流器电路。 桥式整流电路的每个支路包括单个微型二极管或多个微型二极管。 发光器件电连接到AC电源，AC电源在两个电流回路中交替地驱动发光器件。 因此，桥式整流电路的两个电流回路中的微型二极管轮流发光。

    Digital phase-locked loops and frequency adjusting methods thereof
    4.
    发明授权
    Digital phase-locked loops and frequency adjusting methods thereof 有权
    数字锁相环及其频率调整方法

    公开(公告)号：US08325870B2

    公开(公告)日：2012-12-04

    申请号：US12729308

    申请日：2010-03-23

    Applicant: Tse-Peng Chen

    Inventor： Tse-Peng Chen

    IPC: H03L7/08 ,  H03D3/24

    CPC classification number: H03L7/085 ,  H03L7/0891 ,  H03L7/18 ,  H03L2207/50

    Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and −1. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

    Abstract translation: 提供具有相位频率检测器（PFD），3态相位频率检测转换器（3态PFD转换器），环路滤波器和数字压控振荡器的数字锁相环。 PFD接收输入频率和参考频率，并且基于输入频率和参考频率之间的相位差输出第一信号和第二信号。 3态PFD转换器根据第一和第二信号输出3态信号，其中3状态信号呈现在1,0和-1中。 环路滤波器仅基于3态信号输出至少一个控制位。 DCO根据控制位调节输出的振荡频率。

    DIGITAL PHASE-LOCKED LOOPS AND FREQUENCY ADJUSTING METHODS THEREOF
    5.
    发明申请
    DIGITAL PHASE-LOCKED LOOPS AND FREQUENCY ADJUSTING METHODS THEREOF 有权
    数字相位锁定及其频率调节方法

    公开(公告)号：US20110069792A1

    公开(公告)日：2011-03-24

    申请号：US12729308

    申请日：2010-03-23

    Applicant: Tse-Peng Chen

    Inventor： Tse-Peng Chen

    IPC: H04L27/06 ,  H03L7/08

    CPC classification number: H03L7/085 ,  H03L7/0891 ,  H03L7/18 ,  H03L2207/50

    Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and −1. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

    Abstract translation: 提供具有相位频率检测器（PFD），3态相位频率检测转换器（3态PFD转换器），环路滤波器和数字压控振荡器的数字锁相环。 PFD接收输入频率和参考频率，并且基于输入频率和参考频率之间的相位差输出第一信号和第二信号。 3态PFD转换器根据第一和第二信号输出3态信号，其中3状态信号呈现在1,0和-1中。 环路滤波器仅基于3态信号输出至少一个控制位。 DCO根据控制位调节输出的振荡频率。

    Asynchronous first in first out interface and operation method thereof
    7.
    发明授权
    Asynchronous first in first out interface and operation method thereof 有权
    先进先出异步接口及其操作方法

    公开(公告)号：US07996704B2

    公开(公告)日：2011-08-09

    申请号：US11892238

    申请日：2007-08-21

    Applicant: Tse-Peng Chen

    Inventor： Tse-Peng Chen

    IPC: G06F5/06 ,  G06F5/00

    CPC classification number: G06F1/04 ,  G06F13/4059

    Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

    Abstract translation: 本发明提供了异步先进先出（FIFO）接口和操作方法，其中异步FIFO接口的读出时钟和写入时钟是异步的。 异步FIFO接口包括FIFO缓冲器，时钟控制器和可变整数分频器。 FIFO缓冲器至少输入一个具有写入时钟的数据，并输出至少一个具有读出时钟的数据。 时钟控制器根据存储在FIFO缓冲器中的数据数量输出时钟控制信号。 可变整数分频器分割第一信号以通过由时钟控制信号控制的整数除数来产生读出时钟或写入时钟，以便调整存储在FIFO缓冲器中的数据的数量。

    Adjustable digital lock detector
    8.
    发明授权
    Adjustable digital lock detector 有权
    可调数字锁定检测器

    公开(公告)号：US07595672B2

    公开(公告)日：2009-09-29

    申请号：US11861260

    申请日：2007-09-25

    Applicant: Tse-Peng Chen

    Inventor： Tse-Peng Chen

    IPC: H03L7/06

    CPC classification number: H03L7/095

    Abstract: An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.

    Abstract translation: 用于锁相环（PLL）的可调数字锁定检测器具有可变计数器，用于输出对应于第一时钟信号，目标计数数信号和计数数偏移信号的输出信号，用于对输出信号进行采样的锁存器 根据所述输出信号的采样结果输出锁存输出信号;引导/延迟检测器，用于接收所述锁存输出信号，并根据所述锁存输出信号的预定状态输出所述计数数字偏移信号;以及 用于接收锁存器输出信号并根据锁存输出信号和第二时钟信号输出仲裁器输出信号的仲裁器。

    Asynchronous first in first out interface, method thereof and integrated receiver
    9.
    发明授权
    Asynchronous first in first out interface, method thereof and integrated receiver 有权
    先进先出的接口及其接收方法

    公开(公告)号：US08346201B2

    公开(公告)日：2013-01-01

    申请号：US12763281

    申请日：2010-04-20

    Applicant: Tse-Peng Chen

    Inventor： Tse-Peng Chen

    IPC: H04B1/16

    CPC classification number: H04L7/00 ,  G06F5/06 ,  G06F2205/061 ,  H03L7/099 ,  H03L7/18 ,  H03L7/183 ,  H03L2207/06 ,  H04J3/0685 ,  H04L7/005

    Abstract: An asynchronous FIFO interface having a readout clock asynchronous with a write clock is provided. The asynchronous FIFO interface includes a FIFO buffer, a clock controller, a reference source and a signal source. The FIFO buffer receives a digital signal from an ADC according to the write clock and outputs a digital signal to a processor according to the readout clock. The clock controller outputs a clock control signal according to the amount of data stored in the FIFO buffer. The reference source provides an oscillation frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the readout clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency.

    Abstract translation: 提供了具有与写时钟异步的读出时钟的异步FIFO接口。 异步FIFO接口包括FIFO缓冲器，时钟控制器，参考源和信号源。 FIFO缓冲器根据写时钟从ADC接收数字信号，并根据读出时钟将数字信号输出到处理器。 时钟控制器根据存储在FIFO缓冲器中的数据量输出时钟控制信号。 参考源提供振荡频率。 信号源将振荡频率除以第一整数除数以产生参考频率，将读出时钟除以第二整数除数以产生输入频率，并通过将参考频率与输入频率进行比较来输出控制信号。

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