发明授权
- 专利标题： Manufacturing method of semiconductor integrated circuit device
- 专利标题（中）： 半导体集成电路器件的制造方法
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申请号： US11719112申请日： 2004-11-18
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公开(公告)号： US07598100B2公开(公告)日： 2009-10-06
- 发明人: Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka
- 申请人： Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Mattingly & Malur, P.C.
- 国际申请： PCT/JP2004/017160 WO 20041118
- 国际公布： WO2006/054344 WO 20060526
- 主分类号： H01L21/00
- IPC分类号： H01L21/00 ; H01L31/26 ; H01L21/66 ; H01L21/82
摘要：
As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.
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