公开(公告)号：US20110175634A1

公开(公告)日：2011-07-21

申请号：US13075666

申请日：2011-03-30

Applicant: Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

Inventor： Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC: G01R31/3187 ,  G01R31/20

CPC classification number: H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

公开(公告)号：US20100304510A1

公开(公告)日：2010-12-02

申请号：US12853360

申请日：2010-08-10

Applicant: Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

Inventor： Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC: H01L21/66

CPC classification number: H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract translation: 为了允许具有金字塔或梯形金字塔形式的窄间距探针设置的测试焊盘的半导体集成电路器件进行电气测试，是由依次层叠铑膜和镍膜而形成的金属膜形成的。 在互连和金属膜之间的聚酰亚胺膜中形成通孔，并且互连电连接到金属膜。 通过将配备有另一个探针和通孔的另一金属膜的平面图案转过预定角度，获得装配有一个探针和通孔的金属膜之一的平面图案。

公开(公告)号：US20100279502A1

公开(公告)日：2010-11-04

申请号：US12836580

申请日：2010-07-15

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC: H01L21/768

CPC classification number: G01R3/00 ,  G01R1/07342

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract translation: 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US20090130785A1

公开(公告)日：2009-05-21

申请号：US11719112

申请日：2004-11-18

Applicant: Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

Inventor： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R1/0735 ,  G01R3/00

Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

Abstract translation: 随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的​​问题。 为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。 然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

公开(公告)号：US07534629B2

公开(公告)日：2009-05-19

申请号：US11448071

申请日：2006-06-07

Applicant: Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

Inventor： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

IPC: H01L21/66

CPC classification number: G01R1/0735

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract translation: 通过使用通过使用半导体集成电路器件的制造技术形成的膜探针，将提高在多个芯片上共同执行的探测的产量。 通过使用多个推动器形成探针卡，每个推动器由POGO针绝缘体，POGO针，FPC连接器，膜探针HMS，冲击缓冲片，冲击缓冲板，芯片冷凝器YRS等形成 其中一个或两个POGO销按压布置成岛状的多个金属膜。 将一个或多个切口制成与膜探针区域中基本上平行于电连接到形成在膜探针中的探针的布线的延伸方向的方向匹配的待测芯片。

公开(公告)号：US07235413B2

公开(公告)日：2007-06-26

申请号：US10968431

申请日：2004-10-20

Applicant: Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

Inventor： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R3/00 ,  G01R1/07307 ,  G01R31/2889 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

Abstract: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

Abstract translation: 降低在半导体集成电路器件的电气检查时对测试焊盘，层间绝缘膜，半导体元件或布线造成的任何损坏。 在薄膜探针的上表面上形成具有相对于待检查晶片的线膨胀率（热膨胀系数）大致相等的加强筋，在探针上方的加强件中切割槽，比第一弹性体柔软 第二弹性体被布置成填充凹槽并使槽溢出预定量，作为多层布线板的玻璃环氧树脂基板安装在第二弹性体上，并且设置在第二弹性体的上表面上的焊盘 作为属于薄膜探针的布线的一部分的玻璃环氧树脂基板和接合焊盘通过电线电连接。

公开(公告)号：US20060286715A1

公开(公告)日：2006-12-21

申请号：US11471712

申请日：2006-06-21

Applicant: Akio Hasebe ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Shingo Yorisaki ,  Yasuhiro Motoyama

Inventor： Akio Hasebe ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Shingo Yorisaki ,  Yasuhiro Motoyama

IPC: H01L21/00

CPC classification number: G01R3/00 ,  G01R1/07378 ,  G01R31/2889

Abstract: During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and back surface thereof is prepared. An elastomer in the form of a sheet and a polyimide sheet are successively disposed on the main surface of the pressing tool. With th elastomer and the polyimide sheet being electrostatically attracted to the pressing tool, the pressing tool is disposed on a thin-film sheet such that the main surface thereof faces the back surface (the surface opposite to the main surface thereof formed with the probe) of the thin-film sheet. Then, the thin-film sheet with the pressing tool bonded thereto is attached to a probe card.

Abstract translation: 在使用具有通过使用用于半导体集成电路器件的制造技术形成的探针的探针的探针测试期间，确保探针和测试垫之间的可靠接触。 制备具有形成在其中并在其主表面和后表面之间延伸穿过其中的至少一个孔部分的按压工具。 在压制工具的主表面上依次设置片状和聚酰亚胺片形式的弹性体。 利用弹性体，将聚酰亚胺片静电吸引到按压工具上，将压制工具设置在薄膜片上，使得其主表面面向背面（与形成有探针的主表面相反的表面） 的薄膜片。 然后，将与其接合的按压工具的薄膜片安装在探针卡上。

公开(公告)号：US20060094162A1

公开(公告)日：2006-05-04

申请号：US11253575

申请日：2005-10-20

Applicant: Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

Inventor： Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

IPC: H01L21/50

CPC classification number: G01R1/0735 ,  Y10T29/49156

Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

Abstract translation: 在用于与由半导体芯片的集成度增加和半导体芯片的检查而产生的窄间距高密度设置的电极焊盘接触的高精度薄膜探针片中，其中金属 在具有尖锐尖端的微小接触端子周围的周边区域中预先形成相对于端子金属可选择的膜，并以与电极焊盘相同的窄间距高密度地设置。 因此，检查过程中的损坏的发生显着减少，并且可以提供同时实现小型化和耐久性的检查装置。

公开(公告)号：US06707682B2

公开(公告)日：2004-03-16

申请号：US09956909

申请日：2001-09-21

Applicant: Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K118

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract translation: 通过将电源层的电位波动相对于在切换IC器件等而发生的接地层的电位波动转换为基底中的焦耳热而不使用任何部件作为对策来实现高安装密度的低EMI电路 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。

公开(公告)号：US4806725A

公开(公告)日：1989-02-21

申请号：US71325

申请日：1987-07-09

Applicant: Yasunori Narizuka ,  Keiji Mori ,  Akira Yabushita ,  Tsuneaki Kamei ,  Mamoru Morita

Inventor： Yasunori Narizuka ,  Keiji Mori ,  Akira Yabushita ,  Tsuneaki Kamei ,  Mamoru Morita

IPC: H05K3/34 ,  B41J2/335 ,  H05K3/24 ,  H05B1/00

CPC classification number: H05K3/244 ,  B41J2/3351 ,  B41J2/3352 ,  B41J2/3355 ,  B41J2/3357 ,  B41J2/33575 ,  H01L2224/81455 ,  H01L2224/81471 ,  H01L2924/01327

Abstract: A circuit substrate, such as a thermal printing head, having electrodes made of a material suitable for soldering. The electrode to be soldered, at least in part, is composed of an alloy of Ni and Cu, whose composition ranges from 65 mol % Ni - 35 mol % Cu to 75 mol % Ni - 25 mol % Cu.

Abstract translation: 电路基板，例如热敏打印头，具有由适于焊接的材料制成的电极。 待焊接的电极至少部分由Ni和Cu的合金组成，其组成范围为65mol％Ni-35mol％Cu至75mol％Ni-25mol％Cu。