For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.