发明授权
- 专利标题： Method and apparatus for power reduction on a processor bus
- 专利标题（中）： 处理器总线上功率降低的方法和装置
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申请号： US11726910申请日： 2007-03-22
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公开(公告)号： US07623396B2公开(公告)日： 2009-11-24
- 发明人: Chunyu Zhang , Chris D. Matthews
- 申请人： Chunyu Zhang , Chris D. Matthews
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Matthew C. Fagan
- 主分类号： G11C7/00
- IPC分类号： G11C7/00
摘要：
Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.
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