公开(公告)号：US07623396B2

公开(公告)日：2009-11-24

申请号：US11726910

申请日：2007-03-22

申请人： Chunyu Zhang ,  Chris D. Matthews

发明人： Chunyu Zhang ,  Chris D. Matthews

IPC分类号： G11C7/00

CPC分类号： G06F1/32

摘要： Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

摘要翻译： 通过减少地址总线上的地址信号的驱动持续时间来减少地址总线接口的功耗。 地址总线接口可以在正常或省电模式下工作。 在省电模式下，地址信号被驱动四分之一的时钟周期而不是半个时钟周期，并且地址选通沿被移动，使得它们与有效的地址信号对准。

公开(公告)号：US20080288797A1

公开(公告)日：2008-11-20

申请号：US11726910

申请日：2007-03-22

申请人： Chunyu Zhang ,  Chris D. Matthews

发明人： Chunyu Zhang ,  Chris D. Matthews

IPC分类号： G06F1/32

CPC分类号： G06F1/32

摘要： Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals.

摘要翻译： 通过减少地址总线上的地址信号的驱动持续时间来减少地址总线接口的功耗。 地址总线接口可以在正常或省电模式下工作。 在省电模式下，地址信号被驱动四分之一的时钟周期而不是半个时钟周期，并且地址选通沿被移动，使得它们与有效的地址信号对准。

公开(公告)号：US07804890B2

公开(公告)日：2010-09-28

申请号：US11166030

申请日：2005-06-23

申请人： Muraleedhara H. Navada ,  Tim Frodsham ,  Sanjay Dabral ,  Allen Baum ,  Chris D. Matthews ,  Chris C. Gianos ,  Rahul R. Shah ,  Theodore Z. Schoenborn

发明人： Muraleedhara H. Navada ,  Tim Frodsham ,  Sanjay Dabral ,  Allen Baum ,  Chris D. Matthews ,  Chris C. Gianos ,  Rahul R. Shah ,  Theodore Z. Schoenborn

IPC分类号： H04B3/46

CPC分类号： H04L7/10 ,  H04L7/0008 ,  H04L7/0041

摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

摘要翻译： 关于改进对测试矢量的集成设备确定性响应的讨论。 例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。 具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。

公开(公告)号：US07577861B2

公开(公告)日：2009-08-18

申请号：US11322681

申请日：2005-12-30

申请人： Alexander Levin ,  Sriram Badrinarayanan ,  Chris D. Matthews

发明人： Alexander Levin ,  Sriram Badrinarayanan ,  Chris D. Matthews

IPC分类号： G06F13/42 ,  G06F1/00 ,  G06F1/12

CPC分类号： G06F13/4077

摘要： A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.

摘要翻译： 本文描述了将输入数据流串行化为输出数据流的方法和装置。 分别在第一和第二时钟信号的上升沿对第一和第二输入数据流进行采样，以便根据时钟信号的下降沿降低抖动。 第二时钟信号与第一时钟信号相差180度，以在输出数据流的第一单位间隔中采样第一输入数据流，并在输出数据流的第二单位间隔采样第二输入数据流。 因此，序列化的输出数据流以第一和第二输入数据流的频率的两倍被驱动，包括来自输出数据流每个周期的第一和第二输入数据流的逻辑信息。

公开(公告)号：US06963991B2

公开(公告)日：2005-11-08

申请号：US10160621

申请日：2002-05-31

申请人： Kevin M. Hill ,  Chris D. Matthews ,  Amir A. Bashir ,  Kevin E. Arendt ,  Andrew M. Volk

发明人： Kevin M. Hill ,  Chris D. Matthews ,  Amir A. Bashir ,  Kevin E. Arendt ,  Andrew M. Volk

IPC分类号： G06F1/12 ,  G06F1/04

CPC分类号： G06F1/12

摘要： Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

摘要翻译： 本发明的实施例涉及MCH的存储器控​​制集线器（MCH）时钟主机。 通常，在计算机系统中，处理器通过前端总线（FSB）耦合到MCH。 此外，输入/输出控制集线器（ICH）通常通过背面总线或Hub Link耦合到MCH。 在一个实施例中，MCH时钟主机的主机锁相环（HPLL）接收在FSB上发送的FSB时钟信号，并且基于FSB时钟信号产生本地同步时钟信号。 MCH时钟主机的延迟锁定环路（DLL）也接收FSB时钟信号并产生系统时钟信号。 特别地，DLL将系统时钟信号同步到本地同步时钟，并将系统时钟信号驱动到电路板上的许多不同设备。