A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group.