发明授权
US07653889B2 Method and apparatus for repeat execution of delay analysis in circuit design
失效
在电路设计中重复执行延迟分析的方法和装置
- 专利标题： Method and apparatus for repeat execution of delay analysis in circuit design
- 专利标题（中）： 在电路设计中重复执行延迟分析的方法和装置
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申请号： US11524342申请日： 2006-09-20
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公开(公告)号： US07653889B2公开(公告)日： 2010-01-26
- 发明人: Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
- 申请人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
- 申请人地址： JP Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JP Kawasaki
- 代理机构： Fujitsu Patent Center
- 优先权： JP2006-081707 20060323
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; G06F9/45
摘要：
An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
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