A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.