发明授权
- 专利标题： Dual scan chain design method and apparatus
- 专利标题（中）： 双扫链设计方法及装置
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申请号： US10718445申请日： 2003-11-19
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公开(公告)号： US07657809B1公开(公告)日： 2010-02-02
- 发明人: Sandeep Bhatia
- 申请人： Sandeep Bhatia
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Vista IP Law Group, LLP
- 主分类号： G01R31/28
- IPC分类号： G01R31/28
摘要：
A method for testing an integrated circuit includes scanning test data from an input and an output pin into a first scan chain during a first state of a clock cycle, and scanning test data from the same input and output pins into a second scan chain during a second state of the clock cycle.
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