Invention Grant
US07661023B2 System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation
失效
用于验证缓存监听逻辑的系统和方法以及用于处理器设计验证和验证的指令和数据高速缓存之间的一致性
- Patent Title: System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation
- Patent Title (中): 用于验证缓存监听逻辑的系统和方法以及用于处理器设计验证和验证的指令和数据高速缓存之间的一致性
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Application No.: US11779378Application Date: 2007-07-18
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Publication No.: US07661023B2Publication Date: 2010-02-09
- Inventor: Sampan Arora , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Chakrapani Rayadurgam
- Applicant: Sampan Arora , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Chakrapani Rayadurgam
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Van Leeuwen & Van Leeuwen
- Agent Matthew B. Talpis
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.
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