公开(公告)号：US20090070631A1

公开(公告)日：2009-03-12

申请号：US11853130

申请日：2007-09-11

Applicant: Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

Inventor： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

IPC: G06F11/00

CPC classification number: G06F11/263 ,  G06F11/2236

Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

Abstract translation: 提出了一种通过混合测试用例指令顺序从一个测试用例创建多个测试用例场景的系统和方法，同时保持相对子测试用例指令顺序完整。 一个测试用例生成器生成并提供一个包含多个子测试用例的测试用例给测试用例执行器。 反过来，测试用例执行器递归地调度并将不同的混洗指令命令的测试用例调度到处理器，以便有效地测试处理器。 在一个实施例中，测试用例生成器向测试用例执行器提供多个测试用例。 在另一个实施例中，测试用例生成器向多个测试用例执行器提供测试用例，这些测试用例执行器又将洗牌测试用例并将洗牌的测试用例提供给它们各自的处理器。

公开(公告)号：US07661023B2

公开(公告)日：2010-02-09

申请号：US11779378

申请日：2007-07-18

Applicant: Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

Inventor： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

IPC: G06F11/00

CPC classification number: G06F11/263 ,  G06F11/261

Abstract: A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

Abstract translation: 提出了一种用于使用由分支指令创建的指令流“孔”来验证高速缓存监听逻辑和指令高速缓存与数据高速缓存之间的一致性的系统和方法。 测试模式生成器包括将数据加载/存储到指令流孔中的指令。 反过来，通过执行测试模式，处理器线程将L2高速缓存行加载到指令高速缓存（icache）和数据高速缓存（dcache）中。 测试模式根据存储指令修改dcache中的数据。 反过来，本文描述的发明识别窥探逻辑是否检测到改变并相应地更新icache的相应缓存行。

公开(公告)号：US20090070629A1

公开(公告)日：2009-03-12

申请号：US11853170

申请日：2007-09-11

Applicant: Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Sai Rupak Mohanan

Inventor： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Sai Rupak Mohanan

IPC: G06F11/263

CPC classification number: G06F11/263

Abstract: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes.

Abstract translation: 用于生成测试用例和位掩码的系统和方法，允许测试用例执行器使用不同的机器状态寄存器位集多次重新执行测试用例。 测试用例发生器基于识别的不变位和半不变位创建位掩码。 测试用例生成器包括与半不变位对应的补偿值到测试用例中，并将测试用例以及位掩码提供给测试用例执行器。 反过来，测试用例执行器将每个测试用例分配到不同的机器状态寄存器位设置的多个处理器。 每个机器状态寄存器位组将处理器置于不同的模式。

公开(公告)号：US07689886B2

公开(公告)日：2010-03-30

申请号：US11779390

申请日：2007-07-18

Applicant: Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

Inventor： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC: G06F11/00

CPC classification number: G01R31/31813 ,  G01R31/318357 ,  G11C29/56

Abstract: A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution.

Abstract translation: 提出了一种用于预测lwarx（Load Word And Reserve Index form）和stwcx（Store Word Conditional）指令结果的系统和方法。 lwarx指令在地址/粒子上建立一个预留，只有当粒子的预留仍然存在（条件存储）​​时，针对相同地址/粒子的stwcx指令才会成功“成功”。 由于可能由于诸如执行不同的lwarx或ldarx指令（或其他机制）的处理器（或另一个处理器）的情况而丢失预留，这清除了第一个预留并建立了新的预留，因此本文描述了本发明 以确保stwcx成功和失败可预测性的方式构建测试模式。 因此，stwcx指令在测试模式执行期间是可测试的。

公开(公告)号：US07669083B2

公开(公告)日：2010-02-23

申请号：US11853130

申请日：2007-09-11

Applicant: Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

Inventor： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

IPC: G06F11/00

CPC classification number: G06F11/263 ,  G06F11/2236

Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

Abstract translation: 提出了一种通过混合测试用例指令顺序从一个测试用例创建多个测试用例场景的系统和方法，同时保持相对子测试用例指令顺序完整。 一个测试用例生成器生成并提供一个包含多个子测试用例的测试用例给测试用例执行器。 反过来，测试用例执行器递归地调度并将不同的混洗指令命令的测试用例调度到处理器，以便有效地测试处理器。 在一个实施例中，测试用例生成器向测试用例执行器提供多个测试用例。 在另一个实施例中，测试用例生成器向多个测试用例执行器提供测试用例，这些测试用例执行器又将洗牌测试用例并将洗牌的测试用例提供给它们各自的处理器。

公开(公告)号：US20090024894A1

公开(公告)日：2009-01-22

申请号：US12172628

申请日：2008-07-14

Applicant: Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

Inventor： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC: G01R31/28

CPC classification number: G01R31/31813 ,  G01R31/318371 ,  G06F11/263

Abstract: During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.

Abstract translation: 在测试模式构建期间，测试模式生成器伪随机选择所选lwarx指令的地址，并使用伪随机地址将lwarx指令构建成测试模式。 随后，测试模式生成器在使用伪随机地址的lwarx指令之后建立存储指令。 存储指令适于将伪随机地址存储在预定存储器位置。 测试模式生成器还构建一个中断服务程序，用于服务与中断请求相关联的中断; 检查预定的存储位置; 确定所述伪随机地址位于所述预定存储器位置中; 并使用伪随机地址执行随后的lwarx指令。

公开(公告)号：US20090024876A1

公开(公告)日：2009-01-22

申请号：US11779378

申请日：2007-07-18

Applicant: Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

Inventor： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

IPC: G06F11/26

CPC classification number: G06F11/263 ,  G06F11/261

Abstract: A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

Abstract translation: 提出了一种用于使用由分支指令创建的指令流“孔”来验证高速缓存监听逻辑和指令高速缓存与数据高速缓存之间的一致性的系统和方法。 测试模式生成器包括将数据加载/存储到指令流孔中的指令。 反过来，通过执行测试模式，处理器线程将L2高速缓存行加载到指令高速缓存（icache）和数据高速缓存（dcache）中。 测试模式根据存储指令修改dcache中的数据。 反过来，本文描述的发明识别窥探逻辑是否检测到改变并相应地更新icache的相应缓存行。

公开(公告)号：US08127192B2

公开(公告)日：2012-02-28

申请号：US12172628

申请日：2008-07-14

Applicant: Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

Inventor： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/31813 ,  G01R31/318371 ,  G06F11/263

Abstract: During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.

Abstract translation: 在测试模式构建期间，测试模式生成器伪随机选择所选lwarx指令的地址，并使用伪随机地址将lwarx指令构建成测试模式。 随后，测试模式生成器在使用伪随机地址的lwarx指令之后建立存储指令。 存储指令适于将伪随机地址存储在预定存储器位置。 测试模式生成器还构建一个中断服务程序，用于服务与中断请求相关联的中断; 检查预定的存储位置; 确定所述伪随机地址位于所述预定存储器位置中; 并使用伪随机地址执行随后的lwarx指令。

公开(公告)号：US08006221B2

公开(公告)日：2011-08-23

申请号：US11853170

申请日：2007-09-11

Applicant: Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Sai Rupak Mohanan

Inventor： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Sai Rupak Mohanan

IPC: G06F17/50

CPC classification number: G06F11/263

Abstract: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes.

Abstract translation: 用于生成测试用例和位掩码的系统和方法，允许测试用例执行器使用不同的机器状态寄存器位集多次重新执行测试用例。 测试用例发生器基于识别的不变位和半不变位创建位掩码。 测试用例发生器包括与半不变位相对应的补偿值到测试用例中，并将测试用例以及位掩码提供给测试用例执行器。 反过来，测试用例执行器将每个测试用例分配到不同的机器状态寄存器位设置的多个处理器。 每个机器状态寄存器位组将处理器置于不同的模式。

公开(公告)号：US20090024886A1

公开(公告)日：2009-01-22

申请号：US11779390

申请日：2007-07-18

Applicant: Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

Inventor： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC: G11C29/00

CPC classification number: G01R31/31813 ,  G01R31/318357 ,  G11C29/56

Abstract: A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution.

Abstract translation: 提出了一种用于预测lwarx（Load Word And Reserve Index form）和stwcx（Store Word Conditional）指令结果的系统和方法。 lwarx指令在地址/粒子上建立一个预留，只有当粒子的预留仍然存在（条件存储）​​时，针对相同地址/粒子的stwcx指令才会成功“成功”。 由于可能由于诸如执行不同的lwarx或ldarx指令（或其他机制）的处理器（或另一个处理器）的情况而丢失预留，这清除了第一个预留并建立了新的预留，因此本文描述了本发明 以确保stwcx成功和失败可预测性的方式构建测试模式。 因此，stwcx指令在测试模式执行期间是可测试的。