发明授权
- 专利标题: FET bias circuit
- 专利标题(中): FET偏置电路
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申请号: US11994702申请日: 2005-07-05
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公开(公告)号: US07671684B2公开(公告)日: 2010-03-02
- 发明人: Tamaki Honda , Hironori Sakamoto , Kenjiro Okadome
- 申请人: Tamaki Honda , Hironori Sakamoto , Kenjiro Okadome
- 申请人地址: JP
- 专利权人: Japan Radio Co., Ltd.
- 当前专利权人: Japan Radio Co., Ltd.
- 当前专利权人地址: JP
- 代理机构: Cantor Colburn LLP
- 优先权: JP2005-196492 20050705
- 国际申请: PCT/JP2006/313404 WO 20050705
- 国际公布: WO2007/004673 WO 20071101
- 主分类号: H03F3/04
- IPC分类号: H03F3/04
摘要:
A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.
公开/授权文献
- US20090115526A1 FET BIAS CIRCUIT 公开/授权日:2009-05-07
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