发明授权
- 专利标题： CMOS fabrication process
- 专利标题（中）： CMOS制作工艺
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申请号： US12209270申请日： 2008-09-12
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公开(公告)号： US07678637B2公开(公告)日： 2010-03-16
- 发明人: Mahalingam Nandakumar , Song Zhao , Amitabh Jain
- 申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
公开/授权文献
- US20090079008A1 CMOS Fabrication Process 公开/授权日：2009-03-26
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