公开(公告)号：US20140024656A1

公开(公告)日：2014-01-23

申请号：US14008693

申请日：2012-04-01

Applicant: Guisen Zhang ,  Yin Chen ,  Xiangqing Xu ,  Bifeng Liu ,  Xiaojun Feng ,  Song Zhao ,  Shicheng Liu ,  Minquan Yu ,  Yu Lan ,  Yinli Qiu

Inventor： Guisen Zhang ,  Yin Chen ,  Xiangqing Xu ,  Bifeng Liu ,  Xiaojun Feng ,  Song Zhao ,  Shicheng Liu ,  Minquan Yu ,  Yu Lan ,  Yinli Qiu

IPC: C07D417/12 ,  C07D413/14

CPC classification number: C07D417/12 ,  C07D413/14 ,  C07D417/14

Abstract: The present invention belongs to the medicinal chemistry field, and specifically discloses a [1,3,4]oxadiazole derivative with the structure of general formula (I) and pharmaceutically acceptable salt thereof. The compound can be used to prepare a medicine for preventing or treating a disease of the central nervous system.

Abstract translation: 本发明属于药物化学领域，具体公开了具有通式（I）结构的[1,3,4]恶二唑衍生物及其药学上可接受的盐。 该化合物可用于制备用于预防或治疗中枢神经系统疾病的药物。

公开(公告)号：US08125035B2

公开(公告)日：2012-02-28

申请号：US12696215

申请日：2010-01-29

Applicant: Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract translation: 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US20120045147A1

公开(公告)日：2012-02-23

申请号：US13284227

申请日：2011-10-28

Applicant: Yuan Liu ,  Song Zhao ,  Jing Wang

Inventor： Yuan Liu ,  Song Zhao ,  Jing Wang

IPC: G06K9/36

CPC classification number: G06T3/40 ,  G06K9/325

Abstract: An image conversion method, a conversion device, and a display system are provided in the embodiments of the present invention. The image conversion method includes: performing word area detection on an image to acquire a detected word area; and performing conversion processing on the image according to the word area to acquire a converted image that has an aspect ratio different from that of an unconverted image. The conversion device includes: a detection unit, configured to perform word area detection on an image to acquire a detected word area; and a conversion unit, configured to perform conversion processing on the image according to the word area to acquire a converted image that has an aspect ratio different from that of an unconverted image. In this way, an important content area of the image may be retained and clearly displayed.

Abstract translation: 在本发明的实施例中提供了图像转换方法，转换装置和显示系统。 图像转换方法包括：对图像执行字区域检测以获取检测到的字区域; 以及根据所述单词区域对所述图像执行转换处理，以获取具有与未转换图像的宽高比不同的宽高比的转换图像。 转换装置包括：检测单元，被配置为对图像执行字区域检测以获取检测到的字区域; 以及转换单元，被配置为根据所述单词区域对所述图像执行转换处理，以获取具有与未转换图像的宽高比不同的纵横比的转换图像。 以这种方式，图像的重要内容区域可以被保留和清楚地显示。

公开(公告)号：US08101476B2

公开(公告)日：2012-01-24

申请号：US12541335

申请日：2009-08-14

Applicant: Kanan Garg ,  Haowen Bu ,  Mahalingam Nandakumar ,  Song Zhao

Inventor： Kanan Garg ,  Haowen Bu ,  Mahalingam Nandakumar ,  Song Zhao

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843 ,  H01L29/7845

Abstract: A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.

Abstract translation: 一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。 沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。 在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

公开(公告)号：US20090079008A1

公开(公告)日：2009-03-26

申请号：US12209270

申请日：2008-09-12

Applicant: Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract translation: 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US07216310B2

公开(公告)日：2007-05-08

申请号：US10993815

申请日：2004-11-19

Applicant: Amitava Chatterjee ,  David Barry Scott ,  Theodore W. Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

Inventor： Amitava Chatterjee ,  David Barry Scott ,  Theodore W. Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

IPC: G06F17/50 ,  G11C5/14 ,  H03K3/01 ,  G05F1/10

CPC classification number: G06F17/505

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract translation: 本发明提供一种设计电路的方法（100）。 该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

公开(公告)号：US20060189048A1

公开(公告)日：2006-08-24

申请号：US11060841

申请日：2005-02-18

Applicant: Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

Inventor： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

IPC: H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Abstract translation: 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上形成封端的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

公开(公告)号：US07029967B2

公开(公告)日：2006-04-18

申请号：US10896599

申请日：2004-07-21

Applicant: Song Zhao ,  Sue E. Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald S. Miles ,  Duofeng Yue ,  Lance S. Robertson

Inventor： Song Zhao ,  Sue E. Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald S. Miles ,  Duofeng Yue ,  Lance S. Robertson

IPC: H01L21/8238 ,  H01L21/331

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

Abstract translation: 描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。 在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。 植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。 在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

公开(公告)号：US20060019478A1

公开(公告)日：2006-01-26

申请号：US10896599

申请日：2004-07-21

Applicant: Song Zhao ,  Sue Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald Miles ,  Duofeng Yue ,  Lance Robertson

Inventor： Song Zhao ,  Sue Crank ,  Amitava Chatterjee ,  Kaiping Liu ,  Jiong-Ping Lu ,  Donald Miles ,  Duofeng Yue ,  Lance Robertson

IPC: H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

公开(公告)号：US20050149887A1

公开(公告)日：2005-07-07

申请号：US10993815

申请日：2004-11-19

Applicant: Amitava Chatterjee ,  David Scott ,  Theodore Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

Inventor： Amitava Chatterjee ,  David Scott ,  Theodore Houston ,  Song Zhao ,  Shaoping Tang ,  Zhiqiang Wu

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract translation: 本发明提供一种设计电路的方法（100）。 该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。