Invention Grant
US07691752B2 Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
有权
在狭窄隔离有界的源/漏区和由此形成的结构上形成改进的EPI填充的方法
- Patent Title: Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
- Patent Title (中): 在狭窄隔离有界的源/漏区和由此形成的结构上形成改进的EPI填充的方法
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Application No.: US11694458Application Date: 2007-03-30
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Publication No.: US07691752B2Publication Date: 2010-04-06
- Inventor: Pushkar Ranade , Keith Zawadzki , Christopher Auth
- Applicant: Pushkar Ranade , Keith Zawadzki , Christopher Auth
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kathy J. Ortiz
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469 ; H01L29/04
Abstract:
Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.
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