公开(公告)号：US20170062593A1

公开(公告)日：2017-03-02

申请号：US15351169

申请日：2016-11-14

申请人： Pushkar Ranade

发明人： Pushkar Ranade

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/28 ,  H01L29/40 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC分类号： H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/28167 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/31055 ,  H01L21/31604 ,  H01L21/47 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654

摘要： A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

摘要翻译： 描述了形成具有有源区和兼容介质层的半导体结构的方法。 在一个实施例中，半导体结构具有由第一半导体材料的氧化物构成的电介质层，其中在介电层和第一半导体材料之间形成第二（和组成上不同的）半导体材料。 在另一个实施例中，第二半导体材料的一部分被第三半导体材料所替代，以便赋予第二半导体材料的晶格结构单轴应变。

公开(公告)号：US09397165B2

公开(公告)日：2016-07-19

申请号：US15018408

申请日：2016-02-08

申请人： Pushkar Ranade

发明人： Pushkar Ranade

IPC分类号： H01L29/165

CPC分类号： H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/28167 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/31055 ,  H01L21/31604 ,  H01L21/47 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654

摘要： A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

摘要翻译： 描述了形成具有有源区和兼容电介质层的半导体结构的方法。 在一个实施例中，半导体结构具有由第一半导体材料的氧化物构成的电介质层，其中在介电层和第一半导体材料之间形成第二（和组成上不同的）半导体材料。 在另一个实施例中，第二半导体材料的一部分被第三半导体材料所替代，以便赋予第二半导体材料的晶格结构单轴应变。

公开(公告)号：US20160172459A1

公开(公告)日：2016-06-16

申请号：US15018408

申请日：2016-02-08

申请人： Pushkar Ranade

发明人： Pushkar Ranade

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/28167 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/31055 ,  H01L21/31604 ,  H01L21/47 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654

摘要： A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

公开(公告)号：US08883600B1

公开(公告)日：2014-11-11

申请号：US13725152

申请日：2012-12-21

申请人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US08748986B1

公开(公告)日：2014-06-10

申请号：US13559554

申请日：2012-07-26

申请人： Lucian Shifren ,  Pushkar Ranade

发明人： Lucian Shifren ,  Pushkar Ranade

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/786 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78696

摘要： Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.

摘要翻译： 其结构及其制造方法涉及形成在SOI衬底上的改进的绝缘体上半导体（SOI）晶体管。 改进的SOI晶体管包括在源极和漏极之间延伸的基本上未掺杂的沟道，位于基本上未掺杂沟道下方的可选阈值电压设置区域和位于阈值电压设置区域下方的屏蔽区域。 可以使用屏蔽区域和/或阈值电压设置区域的位置和/或掺杂剂浓度来调整改进的SOI晶体管的阈值电压而无需光晕注入或阈值电压注入到沟道中。

公开(公告)号：US20130161743A1

公开(公告)日：2013-06-27

申请号：US13770313

申请日：2013-02-19

申请人： Pushkar Ranade ,  Lucian Shifren ,  Sachin R. Sonkusale

发明人： Pushkar Ranade ,  Lucian Shifren ,  Sachin R. Sonkusale

IPC分类号： H01L29/78 ,  H01L27/085

CPC分类号： H01L29/7816 ,  H01L27/085 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7848

摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及 排水。

公开(公告)号：US20110121404A1

公开(公告)日：2011-05-26

申请号：US12895813

申请日：2010-09-30

申请人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：US07566938B2

公开(公告)日：2009-07-28

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L29/76

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

摘要翻译： 提供了一种制造氧化铪和/或氧化锆膜的方法。 所述方法包括提供溶解，乳化或悬浮在液体中的Hf和/或Zr醇盐的混合物; 至少蒸发醇盐并在大于400℃的温度下沉积蒸发的组分。所​​得膜是致密的，微晶的，并且当在氢等离子体中处理或形成气体退火时能够自钝化。

公开(公告)号：US20090090982A1

公开(公告)日：2009-04-09

申请号：US12316167

申请日：2008-12-10

申请人： Pushkar Ranade ,  Keith Zawadzkl ,  Leif Paulson

发明人： Pushkar Ranade ,  Keith Zawadzkl ,  Leif Paulson

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/36 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

摘要翻译： 本发明公开了一种方法，包括：提供基板; 形成与所述基板上的栅极的两侧相邻的凹陷区域; 在具有两个不同能量和两个不同剂量的两个步骤中进行物种的成角度共同植入到凹陷区域中; 在凹陷区域形成硅锗; 用掺杂剂形成邻近栅极两侧的源极/漏极延伸部分; 并执行退火以激活掺杂剂。

公开(公告)号：US20080237742A1

公开(公告)日：2008-10-02

申请号：US11694458

申请日：2007-03-30

申请人： Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

发明人： Pushkar Ranade ,  Keith Zawadzki ,  Christopher Auth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括等离子体蚀刻晶体管的源极/漏极区域的一部分，然后沿（100）面选择性地湿蚀刻源极漏极区域，以在凹陷源极/漏极区域中形成至少一个（111）区域。