发明授权
- 专利标题: Programmable delay line compensated for process, voltage, and temperature
- 专利标题(中): 可编程延迟线补偿过程,电压和温度
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申请号: US12175399申请日: 2008-07-17
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公开(公告)号: US07701246B1公开(公告)日: 2010-04-20
- 发明人: William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
- 申请人: William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
- 申请人地址: US CA Mountain View
- 专利权人: Actel Corporation
- 当前专利权人: Actel Corporation
- 当前专利权人地址: US CA Mountain View
- 代理机构: Lewis and Roca LLP
- 主分类号: G06F7/38
- IPC分类号: G06F7/38 ; H03K19/173
摘要:
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.