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公开(公告)号:US07701246B1
公开(公告)日:2010-04-20
申请号:US12175399
申请日:2008-07-17
IPC分类号: G06F7/38 , H03K19/173
CPC分类号: H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译: 补偿过程,电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环(DLL),该DLL包括布置为多个级联子串的DLL延迟线 为了响应于数字控制信号,延迟每个子延迟线提供多个延迟量子中的一个。 分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。 数字延迟线被布置为多个级联子延迟线,每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。