Invention Grant
- Patent Title: Stress enhanced transistor and methods for its fabrication
- Patent Title (中): 应力增强晶体管及其制造方法
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Application No.: US11611784Application Date: 2006-12-15
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Publication No.: US07704840B2Publication Date: 2010-04-27
- Inventor: Igor Peidous , Rohit Pal
- Applicant: Igor Peidous , Rohit Pal
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.
Public/Granted literature
- US20080142835A1 STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION Public/Granted day:2008-06-19
Information query
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