发明授权
US07727896B1 Stacked die manufacturing process 有权
堆叠模具制造工艺

  • 专利标题: Stacked die manufacturing process
  • 专利标题(中): 堆叠模具制造工艺
  • 申请号: US12266194
    申请日: 2008-11-06
  • 公开(公告)号: US07727896B1
    公开(公告)日: 2010-06-01
  • 发明人: Arifur Rahman
  • 申请人: Arifur Rahman
  • 申请人地址: US CA San Jose
  • 专利权人: Xilinx, Inc.
  • 当前专利权人: Xilinx, Inc.
  • 当前专利权人地址: US CA San Jose
  • 代理商 Kenneth Glass; Thomas George
  • 主分类号: H01L21/311
  • IPC分类号: H01L21/311
Stacked die manufacturing process
摘要:
A method for forming a stacked-die structure is disclosed in which a buried oxide layer is formed in a semiconductor wafer. Device layers and metal layers are formed on the face side of the semiconductor wafer, defining dice, with each die including an interconnect region. Openings are etched in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer. Conductive material is deposited within the openings so as to form through-die vias. The semiconductor wafer is then attached to a wafer support structure and material is removed from the backside of the semiconductor wafer so as to form an oxide layer having a thickness that is less than the initial thickness of the buried oxide layer. Openings are then etched within the backside of the semiconductor wafer so as to expose the through-die vias, micro-bumps are deposited over the through-die vias, and stacked dice are attached to the micro-bumps so as to electrically couple the stacked dice to the through-die vias. Thereby, a stacked die structure is formed that includes an oxide layer on the backside of the base die. Since the method does not include any high temperature process steps after the semiconductor wafer has been attached to the wafer support structure, thermally-released double-sided tape or adhesive having a low thermal budget can be used to attach the semiconductor wafer to the wafer support structure.
信息查询
IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件;其他类目中不包括的电固体器件(使用半导体器件的测量入G01;一般电阻器入H01C;磁体、电感器、变压器入H01F;一般电容器入H01G;电解型器件入H01G9/00;电池组、蓄电池入H01M;波导管、谐振器或波导型线路入H01P;线路连接器、汇流器入H01R;受激发射器件入H01S;机电谐振器入H03H;扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R;一般电光源入H05B;印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K;在具有特殊应用的电路中使用的半导体器件见应用相关的小类)
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件,例如PN结、耗尽层、载体集结层
H01L21/18 ...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体,如掺杂材料
H01L21/30 ....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的(在半导体材料上制作电极的入H01L21/28)
H01L21/31 .....在半导体材料上形成绝缘层的,例如用于掩膜的或应用光刻技术的(密封层入H01L21/56);以及这些层的后处理;这些层的材料的选择
H01L21/3105 ......后处理
H01L21/311 .......绝缘层的刻蚀
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