发明授权
US07730285B1 Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof
有权
具有部分旁路重排序缓冲器和组合加载/存储算术逻辑单元的数据处理系统及其处理方法
- 专利标题： Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof
- 专利标题（中）： 具有部分旁路重排序缓冲器和组合加载/存储算术逻辑单元的数据处理系统及其处理方法
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申请号： US11497805申请日： 2006-08-02
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公开(公告)号： US07730285B1公开(公告)日： 2010-06-01
- 发明人: Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
- 申请人： Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
- 申请人地址： BM Hamilton
- 专利权人： Marvell International Ltd.
- 当前专利权人： Marvell International Ltd.
- 当前专利权人地址： BM Hamilton
- 主分类号： G06F9/312
- IPC分类号： G06F9/312
摘要：
A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and stores the data, includes at least one bypassable buffer location, and includes at least one non-bypassable buffer location.
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