发明授权
- 专利标题: Method of manufacturing fine features for thin film transistors
- 专利标题(中): 制造薄膜晶体管精细特征的方法
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申请号: US11388731申请日: 2006-03-24
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公开(公告)号: US07749396B2公开(公告)日: 2010-07-06
- 发明人: Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
- 申请人: Eugene M. Chow , William S. Wong , Michael Chabinyc , Ana Claudia Arias
- 申请人地址: US CA Palo Alto
- 专利权人: Palo Alto Research Center Incorporated
- 当前专利权人: Palo Alto Research Center Incorporated
- 当前专利权人地址: US CA Palo Alto
- 代理机构: Fay Sharpe LLP
- 主分类号: H01B13/00
- IPC分类号: H01B13/00 ; C23F1/00
摘要:
A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
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