发明授权
- 专利标题: Method for manufacturing an integrated circuit including an electrolyte material layer
- 专利标题(中): 制造包括电解质材料层的集成电路的方法
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申请号: US11076027申请日: 2005-03-10
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公开(公告)号: US07749805B2公开(公告)日: 2010-07-06
- 发明人: Cay-Uwe Pinnow , Klaus-Dieter Ufert
- 申请人: Cay-Uwe Pinnow , Klaus-Dieter Ufert
- 申请人地址: DE Munich
- 专利权人: Qimonda AG
- 当前专利权人: Qimonda AG
- 当前专利权人地址: DE Munich
- 代理机构: Dicke, Billig & Czaja, PLLC
- 主分类号: H01L21/06
- IPC分类号: H01L21/06
摘要:
A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.
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