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发明授权
US07764215B2 Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing 有权
用于高速低增益比较和高增益自动归零的多级比较器，具有二次差分输入的偏移消除电容

Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing
摘要：
An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要（中）：

模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。

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