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1.发明授权Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC 有权双用比较器/运算放大器用作逐次逼近ADC和DAC公开(公告)号：US07741981B1
公开(公告)日：2010-06-22
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/00
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译： 一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。 一组二进制加权电容器存储模拟输入。 开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。 对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。 分析比较结果以确定模拟输入的最接近的数字值。 在DAC模式下，基于输入数字值切换阵列电容器。 开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。 差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。 可重新配置的比较器级的增益适用于ADC和DAC模式。
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2.发明授权Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing 有权用于高速低增益比较和高增益自动归零的多级比较器，具有二次差分输入的偏移消除电容公开(公告)号：US07764215B2
公开(公告)日：2010-07-27
申请号：US12347113
申请日：2008-12-31
IPC分类号： H03M1/34
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译： 模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。
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3.发明申请DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC 有权双使用比较器/运算放大器，用作两个ADC，DAC和DAC公开(公告)号：US20100164761A1
公开(公告)日：2010-07-01
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译： 一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。 一组二进制加权电容器存储模拟输入。 开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。 对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。 分析比较结果以确定模拟输入的最接近的数字值。 在DAC模式下，基于输入数字值切换阵列电容器。 开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。 差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。 可重新配置的比较器级的增益适用于ADC和DAC模式。
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4.发明授权公开(公告)号：US07999512B2
公开(公告)日：2011-08-16
申请号：US12336514
申请日：2008-12-16
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。
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5.发明授权公开(公告)号：US08643337B2
公开(公告)日：2014-02-04
申请号：US13179107
申请日：2011-07-08
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。
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6.发明授权Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps 有权具有自适应跨导的转换率增益误差放大器和主和辅助放大器共享的单个主导极公开(公告)号：US07795976B2
公开(公告)日：2010-09-14
申请号：US12345862
申请日：2008-12-30
申请人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译： 误差放大器可用于控制功率调节晶体管。 误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。 输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。 当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。 通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。 主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。 串联晶体管增加了增益和输出阻抗。 在放大器中没有使用正反馈的情况下，可靠性提高。
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公开(公告)号：US07705685B2
公开(公告)日：2010-04-27
申请号：US11952127
申请日：2007-12-06
IPC分类号： H03B27/00
CPC分类号： H03K4/501
摘要： An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.
摘要翻译： 振荡器在非常低的电压下工作，但是具有由充电和放电的电容器的比率设定的占空比。 子阈值p沟道晶体管导通低于正常阈值电压的次阈值电流，以及设置复位S-R锁存器的驱动器设置和复位输入。 S-R锁存器驱动振荡器输出。 振荡器输出反馈给对一个电容器板充电的p沟道晶体管。 在半周期中，充电p沟道晶体管截止，允许电容器的一个板通过n沟道放电晶体管放电。 在通过电容器的电容确定的放电周期之后，子阈值p沟道晶体管的栅极对于亚阈值电流流下来足以触发S-R锁存器的置位或复位输入。 由于需要次阈值电流来切换S-R锁存器，所以振荡器开始振荡低于阈值电压。
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8.发明授权Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) 有权具有共模均衡器的零延迟缓冲器，用于输入和反馈差分时钟进入锁相环（PLL）公开(公告)号：US07535272B1
公开(公告)日：2009-05-19
申请号：US11944545
申请日：2007-11-23
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03L7/0891
摘要： A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
摘要翻译： 零延迟时钟发生器具有产生反馈时钟并接收参考时钟的锁相环（PLL）。 所有时钟均为差分并具有共模电压。 外部产生的参考时钟的共模电压可以从内部产生的反馈时钟的共模电压变化。 参考时钟和反馈时钟的共模电压差异导致延迟变化，导致产生的时钟的静态相位偏移。 共模感测和均衡器感测缓冲的参考和反馈时钟的共模电压，并产生控制电压。 控制电压调节接收参考和反馈时钟的差分缓冲器的共模电压和延迟。 控制电压调节差分缓冲器以匹配缓冲参考和反馈时钟的共模电压。 缓冲时钟然后被施加到PLL的相位和频率检测器。
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公开(公告)号：US20090045867A1
公开(公告)日：2009-02-19
申请号：US11838051
申请日：2007-08-13
IPC分类号： H01H85/00
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译： 用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。 因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程 可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。 此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。
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公开(公告)号：US07538597B2
公开(公告)日：2009-05-26
申请号：US11838051
申请日：2007-08-13
IPC分类号： H03H37/76
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译： 用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。 因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程 可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。 此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。
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