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1.发明申请Self-Starting Transistor-Only Full-Wave Rectifier for On-Chip AC-DC Conversion 有权用于片上AC-DC转换的自启动晶体管全波整流器公开(公告)号：US20140104910A1
公开(公告)日：2014-04-17
申请号：US13653016
申请日：2012-10-16
IPC分类号： H02M7/219
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.
摘要翻译： 基于晶体管的全波桥式整流器适用于诸如由射频识别（RFID）设备接收的低交流输入电压。 避免了由桥二极管引起的电压降。 四个p沟道晶体管布置在跨过交流输入的桥中以产生内部电源电压。 比较器接收交流输入并控制升压驱动器的定时，该电压升压驱动器交替地驱动四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 在比较器和升压驱动器运行之前，四个二极管连接的晶体管与四个p沟道桥式晶体管并联连接，以在初始启动期间导通。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。 晶体管桥可以集成到系统芯片上。
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2.发明授权Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权具有自动调零功能的超低压多级高速CMOS比较器公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译： 前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。 前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。 偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。 偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。 反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。 可以添加Kickback电荷隔离晶体管用于电荷隔离。 输出也可以通过均衡的传输门来均衡。 由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。
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3.发明申请Optical Black-Level Cancellation for Optical Sensors Using Open-Loop Sample Calibration Amplifier 有权使用开环采样校准放大器的光学传感器的光学黑电平消除公开(公告)号：US20110221938A1
公开(公告)日：2011-09-15
申请号：US12722148
申请日：2010-03-11
IPC分类号： H04N9/64
CPC分类号： H04N5/361 , H04N5/3575
摘要： A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors and feedback capacitors connect to differential inputs of an amplifier. An accumulating capacitor accumulates voltage differences and generates a common-mode voltage that is fed back to another sampling capacitor that stores an amplifier offset. The sampling capacitor and accumulating capacitor and their associated switches form a discrete-time first-order low-pass filter that filters the pixel voltage during the first phase. In the second phase the amplifier acts as a unity-gain amplifier to output an average of the pixel voltage differences generated during an OBP time when blackened or covered pixels are read from the image sensor.
摘要翻译： 当在外围读取暗像素时，光学黑色像素（OBP）消除电路校正CCD / CMOS图像传感器中的传感器的偏移。 在相同像素脉冲的两个相位期间，将像素电压切换到采样电容器。 采样电容器和反馈电容器连接到放大器的差分输入。 累积电容器累积电压差并产生反馈到存储放大器偏移的另一采样电容器的共模电压。 采样电容器和累加电容器及其相关的开关形成离散时间一阶低通滤波器，其在第一阶段期间对像素电压进行滤波。 在第二阶段，放大器用作单位增益放大器，以输出从图像传感器读取黑化或覆盖像素时在OBP时间期间产生的像素电压差的平均值。
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4.发明授权Self-starting transistor-only full-wave rectifier for on-chip AC-DC conversion 有权用于片内AC-DC转换的自启动晶体管全波整流器公开(公告)号：US08964436B2
公开(公告)日：2015-02-24
申请号：US13653016
申请日：2012-10-16
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.
摘要翻译： 基于晶体管的全波桥式整流器适用于诸如由射频识别（RFID）设备接收的低交流输入电压。 避免了由桥二极管引起的电压降。 四个p沟道晶体管布置在跨过交流输入的桥中以产生内部电源电压。 比较器接收交流输入并控制升压驱动器的定时，该电压升压驱动器交替地驱动四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 在比较器和升压驱动器运行之前，四个二极管连接的晶体管与四个p沟道桥式晶体管并联连接，以在初始启动期间导通。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。 晶体管桥可以集成到系统芯片上。
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5.发明授权CMOS temperature sensor with sensitivity set by current-mirror and resistor ratios without limiting DC bias 有权CMOS温度传感器，灵敏度由电流镜和电阻比设置，不限制直流偏置公开(公告)号：US08864377B2
公开(公告)日：2014-10-21
申请号：US13416728
申请日：2012-03-09
IPC分类号： G01K7/01
摘要： An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.
摘要翻译： 片上温度传感器电路可以在使用PNP晶体管的标准互补金属氧化物半导体（CMOS）工艺中实现。 一对晶体管具有对电压敏感的集电极电流，直接和由于饱和电流。 缩放电阻连接到一个晶体管的发射极，其电压与另一个晶体管的发射极电压相比较，该误差放大器产生与绝对温度成比例的电流源的偏置电压，因为饱和电流灵敏度被减去。 电流被镜像以从输出端吸收电流通过乘法器电阻。 连接在乘法器电阻上的放大器将参考电压进行比较，以独立于温度敏感度设置直流偏置。 温度灵敏度与乘法器电阻和比例电阻的比例成正比，并乘以镜像因子。 还可以提供差分输出。
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6.发明申请CMOS Temperature Sensor with Sensitivity Set by Current-Mirror and Resistor Ratios without Limiting DC Bias 有权CMOS温度传感器，灵敏度由电流镜和电阻比设定，不限制直流偏置公开(公告)号：US20130235903A1
公开(公告)日：2013-09-12
申请号：US13416728
申请日：2012-03-09
IPC分类号： G01K7/01
摘要： An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.
摘要翻译： 片上温度传感器电路可以在使用PNP晶体管的标准互补金属氧化物半导体（CMOS）工艺中实现。 一对晶体管具有对电压敏感的集电极电流，直接和由于饱和电流。 缩放电阻连接到一个晶体管的发射极，其电压与另一个晶体管的发射极电压相比较，该误差放大器产生与绝对温度成比例的电流源的偏置电压，因为饱和电流灵敏度被减去。 电流被镜像以从输出端吸收电流通过乘法器电阻。 连接在乘法器电阻上的放大器将参考电压进行比较，以独立于温度敏感度设置直流偏置。 温度灵敏度与乘法器电阻和比例电阻的比例成正比，并乘以镜像因子。 还可以提供差分输出。
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7.发明授权ESD protection using a capacitivly-coupled clamp for protecting low-voltage core transistors from high-voltage outputs 有权使用电容耦合钳位保护低压核心晶体管免受高压输出的ESD保护公开(公告)号：US08072721B2
公开(公告)日：2011-12-06
申请号：US12481696
申请日：2009-06-10
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018557
摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
摘要翻译： 静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。
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8.发明授权Current-mode-controlled current sensor circuit for power switching converter 有权用于电源开关变换器的电流模式控制电流传感器电路公开(公告)号：US07710094B1
公开(公告)日：2010-05-04
申请号：US12333979
申请日：2008-12-12
CPC分类号： H02M3/156 , G01R19/0092 , H02M2001/0009
摘要： A power converter has a power transistor driving a power current through an inductor to provide a controlled power-supply voltage. The power transistor is on during a first state but off during a second state when a sink transistor reduces the power current through the inductor. Both voltage sensing of the power-supply voltage and current sensing at the power transistor provide feedback to control the amount of time that the first state is active, and thus control the power current. Current sensing is provided by a smaller minor transistor in parallel with the power transistor. The minor transistor turns on after the power transistor to reduce disturbance spikes. Switches connect sources of the power and mirror transistors to an amplifier that drives a sensing transistor. The sensing transistor generates a sensing voltage from the mirror transistor source. During the second state the amplifier's inputs are equalized to provide fast response.
摘要翻译： 功率转换器具有驱动通过电感器的功率电流以提供受控的电源电压的功率晶体管。 功率晶体管在第一状态期间导通，而在第二状态期间，当晶体管晶体管降低通过电感器的功率电流时，功率晶体管截止。 在功率晶体管处的电源电压和电流感测的两个电压检测提供反馈以控制第一状态是有效的时间量，从而控制功率电流。 电流感测由与功率晶体管并联的较小次级晶体管提供。 次晶体管在功率晶体管之后导通，以减少干扰尖峰。 将电源和镜像晶体管的源极连接到驱动感测晶体管的放大器。 感测晶体管产生来自反射镜晶体管源的感测电压。 在第二状态期间，放大器的输入被均衡以提供快速响应。
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9.发明授权Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) 有权具有共模均衡器的零延迟缓冲器，用于输入和反馈差分时钟进入锁相环（PLL）公开(公告)号：US07535272B1
公开(公告)日：2009-05-19
申请号：US11944545
申请日：2007-11-23
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03L7/0891
摘要： A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
摘要翻译： 零延迟时钟发生器具有产生反馈时钟并接收参考时钟的锁相环（PLL）。 所有时钟均为差分并具有共模电压。 外部产生的参考时钟的共模电压可以从内部产生的反馈时钟的共模电压变化。 参考时钟和反馈时钟的共模电压差异导致延迟变化，导致产生的时钟的静态相位偏移。 共模感测和均衡器感测缓冲的参考和反馈时钟的共模电压，并产生控制电压。 控制电压调节接收参考和反馈时钟的差分缓冲器的共模电压和延迟。 控制电压调节差分缓冲器以匹配缓冲参考和反馈时钟的共模电压。 缓冲时钟然后被施加到PLL的相位和频率检测器。
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10.发明授权公开(公告)号：US08797776B2
公开(公告)日：2014-08-05
申请号：US13652474
申请日：2012-10-16
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.
摘要翻译： 桥式整流器在诸如由射频识别（RFID）设备接收的低交流输入电压下工作。 避免了由桥二极管引起的电压降。 四个P沟道晶体管布置在跨越交流输入的晶体管桥中以产生内部电源电压。 另外四个二极管连接的晶体管形成起始二极管电桥，产生比较器电源电压和参考地。 在比较器和升压驱动器运行之前，起动二极管桥即使在初始启动期间也工作。 比较器接收交流输入并且控制升压驱动器的定时，其交替地驱动晶体管桥中的四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。
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