Invention Grant
US07767563B2 Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure
有权
在薄硅晶片上形成硅化物层的方法以及相关的半导体结构
- Patent Title: Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure
- Patent Title (中): 在薄硅晶片上形成硅化物层的方法以及相关的半导体结构
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Application No.: US11726284Application Date: 2007-03-21
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Publication No.: US07767563B2Publication Date: 2010-08-03
- Inventor: Eric J. Li
- Applicant: Eric J. Li
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kenneth A. Nelson
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/44 ; H01L21/336
Abstract:
A semiconducting structure includes a thinned silicon substrate (110), a silicide layer (120) over the thinned silicon substrate, a metal layer (130) over the silicide layer, a solder interface layer (140) over the metal layer, and a cap layer (150) over the solder interface layer. The thinned silicon substrate is no thicker than approximately 500 micrometers. The silicide layer is formed using a rapid thermal processing procedure that locally heats the interface between the metal layer and the silicon substrate but causes no more than negligible thermal impact to other areas of the silicon wafer.
Public/Granted literature
- US20080230911A1 Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure Public/Granted day:2008-09-25
Information query
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