Invention Grant
- Patent Title: Semiconductor die package including embedded flip chip
- Patent Title (中): 半导体芯片封装包括嵌入式倒装芯片
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Application No.: US12047028Application Date: 2008-03-12
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Publication No.: US07768108B2Publication Date: 2010-08-03
- Inventor: Yong Liu , Jeff Ju , Zhongfa Yuan , Roger Luo
- Applicant: Yong Liu , Jeff Ju , Zhongfa Yuan , Roger Luo
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Townsend and Townsend and Crew LLP
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die.
Public/Granted literature
- US20090230537A1 SEMICONDUCTOR DIE PACKAGE INCLUDING EMBEDDED FLIP CHIP Public/Granted day:2009-09-17
Information query
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