Invention Grant
- Patent Title: Pulse latch circuit and semiconductor integrated circuit
- Patent Title (中): 脉冲锁存电路和半导体集成电路
-
Application No.: US12171957Application Date: 2008-07-11
-
Publication No.: US07768294B2Publication Date: 2010-08-03
- Inventor: Yasuhisa Shimazaki , Masakazu Nishibori
- Applicant: Yasuhisa Shimazaki , Masakazu Nishibori
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2005-161010 20050601
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
Public/Granted literature
- US20090024861A1 PULSE LATCH CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2009-01-22
Information query