发明授权
US07768836B2 Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits
有权
通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
- 专利标题: Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits
- 专利标题(中): 通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
-
申请号: US12249678申请日: 2008-10-10
-
公开(公告)号: US07768836B2公开(公告)日: 2010-08-03
- 发明人: Yan Li , Yupin Kawing Fong , Siu Lung Chan
- 申请人: Yan Li , Yupin Kawing Fong , Siu Lung Chan
- 申请人地址: US CA Milpitas
- 专利权人: Sandisk Corporation
- 当前专利权人: Sandisk Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Davis Wright Tremaine LLP
- 主分类号: G11C11/34
- IPC分类号: G11C11/34 ; G11C16/04 ; G11C16/06
摘要:
A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
公开/授权文献
信息查询