公开(公告)号：US20110222345A1

公开(公告)日：2011-09-15

申请号：US13114481

申请日：2011-05-24

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US07894273B2

公开(公告)日：2011-02-22

申请号：US12407665

申请日：2009-03-19

申请人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

发明人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

摘要翻译： 一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。 在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。 这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。 当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。 什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。 当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。 由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

公开(公告)号：US07768836B2

公开(公告)日：2010-08-03

申请号：US12249678

申请日：2008-10-10

申请人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

发明人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

摘要翻译： 一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。 在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。 这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。 当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。 什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。 当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。 由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

公开(公告)号：US20100091573A1

公开(公告)日：2010-04-15

申请号：US12249678

申请日：2008-10-10

申请人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

发明人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

摘要翻译： 一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。 在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。 这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。 当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。 什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。 当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。 由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

公开(公告)号：US07609556B2

公开(公告)日：2009-10-27

申请号：US11955624

申请日：2007-12-13

申请人： Siu Lung Chan

发明人： Siu Lung Chan

IPC分类号： G11C16/06

CPC分类号： G11C8/08 ,  G11C8/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

摘要： In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

摘要翻译： 在编程包括交替地应用编程脉冲和验证编程的非易失性存储器中，当根据存储器单元的状态，验证操作的一部分被识别为多余且被跳过时，节省了时间 。 优选地，在相对于用于在两个存储器状态之间划分的分界阈值电平的程序验证操作中，验证操作包括两个验证子周期的序列，第一子周期相对于预定的第一阈值电平执行验证 边界低于分界阈值水平，第二子周期相对于与分界阈值水平相同的第二阈值水平执行验证。 与常规情况不同，直到组中的任何一个存储单元已被验证通过第一阈值之前才执行第二子周期。

公开(公告)号：US20090103369A1

公开(公告)日：2009-04-23

申请号：US12342679

申请日：2008-12-23

申请人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

发明人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC分类号： G11C16/06 ,  G11C11/10

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

摘要翻译： 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US07471575B2

公开(公告)日：2008-12-30

申请号：US11781917

申请日：2007-07-23

申请人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

发明人： Raul-Adrian Cernea ,  Yan Li ,  Shahzad Khalid ,  Siu Lung Chan

IPC分类号： G11C7/10

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

摘要翻译： 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 多个读/写电路被组织成一组类似的组件堆叠。 考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。 处理器由输入逻辑，锁存器和输出逻辑实现。 输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。 输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。 这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

公开(公告)号：US20130250687A1

公开(公告)日：2013-09-26

申请号：US13429851

申请日：2012-03-26

申请人： Siu Lung Chan

发明人： Siu Lung Chan

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24

摘要： Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell.

摘要翻译： 描述了利用共享位线NAND架构来操作非易失性存储系统的方法。 共享位线NAND架构包括一对或多对NAND串，其中每对一对或多对NAND串共享公共位线。 在一些实施例中，一对NAND串包括与偶数NAND串相邻的奇数NAND串。 在编程与偶数NAND串相关联的存储单元之前，与奇数NAND串相关联的奇数通道（即，未被选择用于编程的该对的NAND串）被预充电到位线禁止电压，漂移和 然后升高到大于位线禁止电压的第二电压，因为与偶数NAND串相关联的偶数通道被预充电。 随后，在编程存储器单元之前，奇数通道可被升压（例如通过自升压）。

公开(公告)号：US08228741B2

公开(公告)日：2012-07-24

申请号：US13029848

申请日：2011-02-17

申请人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

发明人： Yan Li ,  Yupin Kawing Fong ,  Siu Lung Chan

IPC分类号： G11C11/36 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.

摘要翻译： 一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。 在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。 这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。 当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。 什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。 当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。 由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

公开(公告)号：US07593277B2

公开(公告)日：2009-09-22

申请号：US12020449

申请日：2008-01-25

申请人： Siu Lung Chan ,  Raul-Adrian Cernea

发明人： Siu Lung Chan ,  Raul-Adrian Cernea

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/04 ,  G11C7/067 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2216/14 ,  G11C2216/22

摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.

摘要翻译： 用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。 在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。 在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。 当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。