Invention Grant
- Patent Title: Strategy to verify asynchronous links across chips
- Patent Title (中): 跨芯片验证异步链接的策略
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Application No.: US12235532Application Date: 2008-09-22
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Publication No.: US07770051B2Publication Date: 2010-08-03
- Inventor: Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
- Applicant: Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F17/50

Abstract:
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
Public/Granted literature
- US20090016381A1 Strategy to Verify Asynchronous Links Across Chips Public/Granted day:2009-01-15
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