发明授权
US07781765B2 Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask
有权
用于结晶多晶硅的掩模和使用掩模形成薄膜晶体管的方法
- 专利标题: Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask
- 专利标题(中): 用于结晶多晶硅的掩模和使用掩模形成薄膜晶体管的方法
-
申请号: US11737245申请日: 2007-04-19
-
公开(公告)号: US07781765B2公开(公告)日: 2010-08-24
- 发明人: Myung-Koo Kang , Hyun-Jae Kim , Sook-Young Kang
- 申请人: Myung-Koo Kang , Hyun-Jae Kim , Sook-Young Kang
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: F. Chau & Associates, LLC
- 主分类号: H01L29/04
- IPC分类号: H01L29/04
摘要:
A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while baring the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.
公开/授权文献
信息查询
IPC分类: