公开(公告)号：US07217642B2

公开(公告)日：2007-05-15

申请号：US10495673

申请日：2002-01-24

申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

IPC分类号： H01L21/20

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S260/35

摘要： A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.

摘要翻译： 用于形成多晶硅的掩模具有第一狭缝区域，其中垂直方向上布置多个水平狭缝图案，同时承载相同的宽度，在垂直方向上布置多个水平狭缝图案的第二狭缝区域，同时承载相同的宽度 宽度，在垂直方向上布置多个水平狭缝图案同时具有相同宽度的第三狭缝区域，以及沿垂直方向布置多个水平狭缝图案的第四狭缝区域，同时承载相同的宽度。 布置在第一至第四狭缝区域的狭缝图案在第一狭缝区域上与狭缝图案的宽度d成一定比例地沿水平方向的宽度依次增大。 沿水平方向布置在第一至第四狭缝区域处的狭缝图案的中心位于相同的线上。 在垂直方向的各个狭缝区域上排列的狭缝图案彼此间隔8 * d。 或者，第一至第四狭缝区域可以以相反的顺序或在垂直方向上布置。

公开(公告)号：US07183574B2

公开(公告)日：2007-02-27

申请号：US10500514

申请日：2003-01-03

申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

IPC分类号： H01L21/00

CPC分类号： H01L29/42384 ,  G02F1/13454 ,  G02F2202/104 ,  H01L21/02675 ,  H01L21/2026 ,  H01L29/78675

摘要： The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed. In a liquid crystal display according to the present invention, a plurality of thin film transistors forming a data driver circuit include thin films of polycrystalline silicon formed by sequential lateral solidification, at least one portion of a gate electrode of each thin film transistor extends in a direction crossing the grain growing direction, and at least one of the plurality of thin film transistors has a gate electrode having a pattern different from other thin film transistors.

摘要翻译： 本发明涉及薄膜晶体管和液晶显示器。 栅电极被形成为包括沿垂直于增益生长方向的方向延伸的至少一个部分，以使TFT的电荷迁移率均匀，而不增加驱动电路的尺寸。 根据本发明的薄膜晶体管包括在绝缘基板上具有含有生长晶粒的多晶硅薄膜的半导体图案。 半导体图案包括沟道区和相对于沟道区相反的源极和漏极区。 栅极绝缘层覆盖半导体图案。 在栅极绝缘层上形成栅电极，该栅电极具有沿与晶粒的生长方向交叉的方向延伸的至少一部分，与沟道区重叠。 在根据本发明的液晶显示器中，形成数据驱动电路的多个薄膜晶体管包括通过顺序横向固化形成的多晶硅薄膜，每个薄膜晶体管的栅电极的至少一部分以 方向与晶粒生长方向交叉，并且多个薄膜晶体管中的至少一个具有与其它薄膜晶体管不同的图案的栅电极。

公开(公告)号：US20090224262A1

公开(公告)日：2009-09-10

申请号：US12469256

申请日：2009-05-20

申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Woo-Suk Chung

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/42384 ,  G02F1/13454 ,  G02F2202/104 ,  H01L21/02675 ,  H01L21/2026 ,  H01L29/78675

摘要： A thin film transistor and a liquid crystal display, in which a gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed. In a liquid crystal display, a plurality of thin film transistors forming a data driver circuit include thin films of polycrystalline silicon formed by sequential lateral solidification, at least one portion of a gate electrode of each thin film transistor extends in a direction crossing the grain growing direction, and at least one of the plurality of thin film transistors has a gate electrode having a pattern different from other thin film transistors.

摘要翻译： 一种薄膜晶体管和液晶显示器，其中栅极形成为包括沿垂直于增益生长方向的方向延伸的至少一个部分，以使TFT的电荷迁移率均匀，而不增加驱动尺寸 电路。 根据本发明的薄膜晶体管包括在绝缘基板上具有含有生长晶粒的多晶硅薄膜的半导体图案。 半导体图案包括沟道区和相对于沟道区相反的源极和漏极区。 栅极绝缘层覆盖半导体图案。 在栅极绝缘层上形成栅电极，该栅电极具有沿与晶粒的生长方向交叉的方向延伸的至少一部分，与沟道区重叠。 在液晶显示器中，形成数据驱动电路的多个薄膜晶体管包括通过顺序横向固化形成的多晶硅薄膜，每个薄膜晶体管的栅电极的至少一部分沿与晶粒生长相交的方向延伸 并且多个薄膜晶体管中的至少一个薄膜晶体管具有栅极，其具有与其它薄膜晶体管不同的图案。

公开(公告)号：US20080115718A1

公开(公告)日：2008-05-22

申请号：US11866617

申请日：2007-10-03

申请人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

发明人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

IPC分类号： C30B28/08 ,  B32B3/10

CPC分类号： H01L21/02678 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1285 ,  H01L27/1296 ,  Y10T428/24273

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上沉积非晶硅层; 通过使用掩模的多个激光照射将非晶硅层转化为多晶硅层; 在所述多晶硅层上形成栅极绝缘层; 在所述栅极绝缘层上形成多个栅极线; 在栅极线上形成第一层间绝缘层; 在所述第一层间绝缘层上形成多条数据线; 在数据线上形成第二层间绝缘层; 以及在所述第二层间绝缘层上形成多个像素电极，其中所述掩模包括以混合方式布置的多个透射区域和多个阻挡区域。

公开(公告)号：US20050037550A1

公开(公告)日：2005-02-17

申请号：US10493038

申请日：2002-07-09

申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Cheol-Ho Park

发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang ,  Cheol-Ho Park

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/78675

摘要： In a method of manufacturing a thin film transistor according to the present invention, an amorphous silicon thin film is firstly formed on an insulating substrate and a planarization layer is formed thereon. Thereafter, the amorphous silicon thin film is crystallized by a solidification process using a laser-irradiation to form a polysilicon thin film. Next, the polysilicon thin film and the planarization layer are patterned to form a semiconductor layer, and a gate insulating layer covering the semiconductor layer is formed. Then, a gate electrode is formed on the gate insulating layer opposite the semiconductor layer. Next, impurities are implanted into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode, and a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, are formed.

摘要翻译： 在本发明的薄膜晶体管的制造方法中，首先在绝缘基板上形成非晶硅薄膜，在其上形成平坦化层。 此后，通过使用激光照射的固化工艺使非晶硅薄膜结晶，形成多晶硅薄膜。 接下来，对多晶硅薄膜和平坦化层进行构图以形成半导体层，并且形成覆盖半导体层的栅极绝缘层。 然后，在与半导体层相对的栅极绝缘层上形成栅电极。 接下来，将杂质注入到半导体层中以形成相对于栅电极相对的源极区域和漏极区域，并且分别与源极区域和漏极区域电连接的源极电极和漏极电极 形成。

公开(公告)号：US07781765B2

公开(公告)日：2010-08-24

申请号：US11737245

申请日：2007-04-19

申请人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

发明人： Myung-Koo Kang ,  Hyun-Jae Kim ,  Sook-Young Kang

IPC分类号： H01L29/04

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S260/35

摘要： A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while baring the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.

摘要翻译： 用于形成多晶硅的掩模具有第一狭缝区域，其中垂直方向上布置多个水平狭缝图案，同时承载相同的宽度;第二狭缝区域，其中沿垂直方向布置多个水平狭缝图案，同时使其相同 宽度，在垂直方向上布置多个水平狭缝图案同时具有相同宽度的第三狭缝区域，以及沿垂直方向布置多个水平狭缝图案的第四狭缝区域，同时承载相同的宽度。 布置在第一至第四狭缝区域的狭缝图案在第一狭缝区域上与狭缝图案的宽度d成一定比例地沿水平方向的宽度依次增大。 沿水平方向布置在第一至第四狭缝区域处的狭缝图案的中心位于相同的线上。 在垂直方向的各个狭缝区域上排列的狭缝图案间隔8 * d。 或者，第一至第四狭缝区域可以以相反的顺序或在垂直方向上布置。

公开(公告)号：US07294857B2

公开(公告)日：2007-11-13

申请号：US11048726

申请日：2005-02-03

申请人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

发明人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

IPC分类号： H01L29/04

CPC分类号： H01L21/02678 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1285 ,  H01L27/1296 ,  Y10T428/24273

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上沉积非晶硅层; 通过使用掩模的多个激光照射将非晶硅层转化为多晶硅层; 在所述多晶硅层上形成栅极绝缘层; 在所述栅极绝缘层上形成多个栅极线; 在所述栅极线上形成第一层间绝缘层; 在所述第一层间绝缘层上形成多条数据线; 在数据线上形成第二层间绝缘层; 以及在所述第二层间绝缘层上形成多个像素电极，其中所述掩模包括以混合方式布置的多个透射区域和多个阻挡区域。

公开(公告)号：US07164153B2

公开(公告)日：2007-01-16

申请号：US10521345

申请日：2003-11-04

申请人： Su-Gyeong Lee ,  Sook-Young Kang ,  Myung-Koo Kang ,  Hyun-Jae Kim ,  James S. Im

发明人： Su-Gyeong Lee ,  Sook-Young Kang ,  Myung-Koo Kang ,  Hyun-Jae Kim ,  James S. Im

IPC分类号： H01L29/04

CPC分类号： H01L27/1214 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/78645

摘要： A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.

摘要翻译： 提供一种薄膜晶体管阵列面板，其包括：包括多个像素区域的基板; 半导体层，形成在所述基板上，并且在各像素区域中包括多对第一和第二半导体部分; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅极线; 形成在栅极线上的第二绝缘层; 形成在所述第二绝缘层上的数据线; 形成在数据线上的第三绝缘层; 形成在第三绝缘层上并连接到数据线的像素电极，其中第一和第二半导体部分中的至少一个的宽度和长度在至少两个像素区域之间变化。

公开(公告)号：US20060102902A1

公开(公告)日：2006-05-18

申请号：US10521345

申请日：2003-11-04

申请人： Su-Gyeong Lee ,  Sook-Young Kang ,  Myung-Koo Kang ,  Hyun-Jae Kim ,  James Im

发明人： Su-Gyeong Lee ,  Sook-Young Kang ,  Myung-Koo Kang ,  Hyun-Jae Kim ,  James Im

IPC分类号： H01L29/76

CPC分类号： H01L27/1214 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/78645

摘要： A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer; a third insulating layer formed on the data wire; a pixel electrode formed on the third insulating layer and connected to the data wire, wherein width and length of at least one of the first and the second semiconductor portions vary between at least two pixel areas.

摘要翻译： 提供一种薄膜晶体管阵列面板，其包括：包括多个像素区域的基板; 半导体层，形成在所述基板上，并且在各像素区域中包括多对第一和第二半导体部分; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅极线; 形成在栅极线上的第二绝缘层; 形成在所述第二绝缘层上的数据线; 形成在数据线上的第三绝缘层; 形成在第三绝缘层上并连接到数据线的像素电极，其中第一和第二半导体部分中的至少一个的宽度和长度在至少两个像素区域之间变化。

公开(公告)号：US20050151196A1

公开(公告)日：2005-07-14

申请号：US11048726

申请日：2005-02-03

申请人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

发明人： Hyun-Jae Kim ,  Sook-Young Kang ,  Dong-Byum Kim ,  Su-Gyeong Lee ,  Myung-Koo Kang

IPC分类号： H01L51/50 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/12 ,  H01L27/32 ,  H01L29/04 ,  H01L29/786 ,  H01L29/788 ,  H01L31/036 ,  H01L31/0392 ,  H01L31/20 ,  H05B33/14

CPC分类号： H01L21/02678 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1285 ,  H01L27/1296 ,  Y10T428/24273

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上沉积非晶硅层; 通过使用掩模的多个激光照射将非晶硅层转化为多晶硅层; 在所述多晶硅层上形成栅极绝缘层; 在所述栅极绝缘层上形成多个栅极线; 在栅极线上形成第一层间绝缘层; 在所述第一层间绝缘层上形成多条数据线; 在数据线上形成第二层间绝缘层; 以及在所述第二层间绝缘层上形成多个像素电极，其中所述掩模包括以混合方式布置的多个透射区域和多个阻挡区域。