发明授权
- 专利标题： Shadow pipeline in an auxiliary processor unit controller
- 专利标题（中）： 阴影管线在辅助处理器单元控制器中
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申请号： US12057353申请日： 2008-03-27
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公开(公告)号： US07788470B1公开(公告)日： 2010-08-31
- 发明人: Kathryn S. Purcell , Ahmad R. Ansari , Gaurav Gupta
- 申请人： Kathryn S. Purcell , Ahmad R. Ansari , Gaurav Gupta
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 W. Eric Webostad; Thomas George
- 主分类号： G06F9/00
- IPC分类号： G06F9/00
摘要：
A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.