公开(公告)号：US20150188545A1

公开(公告)日：2015-07-02

申请号：US14141469

申请日：2013-12-27

Applicant: Gaurav Gupta ,  Shiva Belwal ,  Ashish Goel

Inventor： Gaurav Gupta ,  Shiva Belwal ,  Ashish Goel

IPC: H03K19/173 ,  H03K3/037

CPC classification number: H03K19/1733 ,  H03K3/037 ,  H03K3/356026 ,  H03K3/35606 ,  H03K3/356078 ,  H03K19/1736

Abstract: A configurable flip-flop circuit has modifiable connections between its circuit elements that allow it to be modified for primary and secondary uses. For example, the flip-flop circuit can be modified to provide secondary functions of NOR and NAND gates during an implementation of an ECO. At other times, the flip-flop circuit can be used to deliver normal flip-flop functionality. A configurable latch circuit is provided that can be modified to provide an output signal or an inverted output signal. A scan circuit is provided that can provide the functionality of a multiplexer.

Abstract translation: 可配置的触发器电路在其电路元件之间具有可修改的连接，允许对其进行一次和二次使用的修改。 例如，触发器电路可以被修改以在ECO的实现期间提供NOR和NAND门的次要功能。 在其他时间，触发器电路可用于提供正常的触发器功能。 提供了可配置的锁存电路，其可以被修改以提供输出信号或反相输出信号。 提供了可以提供多路复用器的功能的扫描电路。

公开(公告)号：US08682860B2

公开(公告)日：2014-03-25

申请号：US13572434

申请日：2012-08-10

Applicant: Robin Kumar Das ,  Ledio Ago ,  Declan Gerard Shanaghy ,  Gaurav Gupta

Inventor： Robin Kumar Das ,  Ledio Ago ,  Declan Gerard Shanaghy ,  Gaurav Gupta

IPC: G06F17/30

CPC classification number: H04L63/105 ,  G06F9/4887 ,  G06F9/5088 ,  G06F17/30091 ,  G06F17/30094 ,  G06F17/30117 ,  G06F17/30289 ,  G06F17/30321 ,  G06F17/30336 ,  G06F17/30864 ,  G06F17/3087 ,  G06F17/30876 ,  G06F17/30896 ,  G06F17/30946 ,  G06F21/6218 ,  G06Q20/145 ,  H04L12/1435 ,  H04L63/10 ,  H04L67/1097

Abstract: Embodiments are directed towards a system and method for a cloud-based front end that may abstract and enable access to the underlying cloud-hosted elements and objects that may be part of a multi-tenant application, such as a search application. Search objects may be employed to access indexed objects. An amount of indexed data accessible to a user may be based on an index storage limit selected by the user, such that data that exceeds the index storage limit may continue to be indexed. Also, one or more projects can be elastically scaled for a user to provide resources that may meet the specific needs of each project.

公开(公告)号：US08645897B1

公开(公告)日：2014-02-04

申请号：US13735054

申请日：2013-01-07

Applicant: Nandini ,  Gaurav Gupta ,  Rohit Srivastava

Inventor： Nandini ,  Gaurav Gupta ,  Rohit Srivastava

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/66

Abstract: An integrated circuit (IC) design verification system includes a memory for storing an IC design and a processor in communication with the memory. The IC design includes multiple IP cores and the design verification apparatus includes multiple verification modules. The processor configures a first set of connections between the IP cores and the verification modules based on a first connection database and verifies each IP core independently using the first set of connections. Thereafter, the processor configures a second set of connections between the IP cores and the verification modules based on a second connection database generated based on the first connection database, and verifies the multiple IP cores together using the second set of connections.

Abstract translation: 集成电路（IC）设计验证系统包括用于存储IC设计的存储器和与存储器通信的处理器。 IC设计包括多个IP核，设计验证装置包括多个验证模块。 处理器基于第一连接数据库配置IP核和验证模块之间的第一组连接，并使用第一组连接独立地验证每个IP核。 此后，处理器基于基于第一连接数据库生成的第二连接数据库来配置IP核和验证模块之间的第二组连接，并且使用第二组连接来验证多个IP内核。

公开(公告)号：US08226422B2

公开(公告)日：2012-07-24

申请号：US12975676

申请日：2010-12-22

Applicant: Pongpinit Towashiraporn ,  Paul B. Crosbie ,  Gaurav Gupta ,  Maninder S. Sehmbey ,  Michael F. Spence

Inventor： Pongpinit Towashiraporn ,  Paul B. Crosbie ,  Gaurav Gupta ,  Maninder S. Sehmbey ,  Michael F. Spence

IPC: H01R12/00

CPC classification number: H01R13/04 ,  H01R13/41

Abstract: An improved plug connector (100) is disclosed. It includes: a generally U-shaped contact (102) including a first vertical leg (104), a second vertical leg (106) and a horizontal leg (108) connecting the first vertical leg (104)and the second vertical leg (106), the first vertical leg (104) being longer than the second vertical leg (106); and a retention block 110 connected to both sides (112) and (114) of the horizontal leg (108) configured to support the U-shaped contact (102).This design can stand up to the harsh environment that it will be exposed to and will provide improved resistance to failure.

Abstract translation: 公开了改进的插头连接器（100）。 它包括：大致U形的接触件（102），包括第一垂直腿部（104），第二垂直腿部（106）和连接第一垂直腿部（104）和第二垂直腿部（106）的水平腿部 ），所述第一垂直腿（104）比所述第二垂直腿（106）长; 以及连接到所述水平腿部（108）的两侧（112）和（114）的保持块110，所述水平腿部构造成支撑所述U形接触件（102）。所述设计可以抵抗将暴露于其的恶劣环境 并将提供改善的故障抵抗力。

公开(公告)号：US08041956B1

公开(公告)日：2011-10-18

申请号：US12857337

申请日：2010-08-16

Applicant: Conor Robert White ,  Michael Peirce ,  Gaurav Gupta

Inventor： Conor Robert White ,  Michael Peirce ,  Gaurav Gupta

IPC: G06F21/00

CPC classification number: H04L63/0861 ,  G06F21/32 ,  G06F2221/2115 ,  G06F2221/2117 ,  G06K9/00073 ,  G06K9/00093 ,  G06K9/72

Abstract: A method of authentication is provided that includes capturing biometric data for a desired biometric type from an individual, determining an algorithm for converting the biometric data into authentication words, converting the captured biometric data into authentication words in accordance with the determined algorithm, including the authentication words in a probe, and comparing the probe against identity records stored in a server system. Each of the identity records includes enrollment biometric words of an individual obtained during enrollment. Moreover, the method includes identifying at least one of the identity records as a potential matching identity record when at least one of the authentication words included in the probe matches at least one of the enrollment biometric words included in the at least one identity record, and generating a list of potential matching identity records.

Abstract translation: 提供了一种认证方法，其包括从个体捕获期望的生物特征类型的生物特征数据，确定用于将生物统计数据转换成认证字的算法，根据所确定的算法将捕获的生物统计数据转换成认证字，包括认证 探针中的单词，以及将探针与存储在服务器系统中的身份记录进行比较。 每个身份记录包括在注册期间获得的个人的登记生物特征词。 而且，当包括在探测器中的认证字中的至少一个与至少一个身份记录中包括的登记生物识别词中的至少一个匹配时，该方法包括将身份记录中的至少一个标识为潜在的匹配身份记录，以及 生成潜在的匹配身份记录列表。

公开(公告)号：US07788470B1

公开(公告)日：2010-08-31

申请号：US12057353

申请日：2008-03-27

Applicant: Kathryn S. Purcell ,  Ahmad R. Ansari ,  Gaurav Gupta

Inventor： Kathryn S. Purcell ,  Ahmad R. Ansari ,  Gaurav Gupta

IPC: G06F9/00

CPC classification number: G06F9/3855 ,  G06F9/3857 ,  G06F9/3877

Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract translation: 描述了用于支持指令执行不正常的方法和控制器。 微处理器经由控制器耦合到协处理器。 微处理器和控制器接收到指令。 分别与指令相关联的指示由微处理器产生，并且指令从第一个队列弹出，以供协处理器执行。 控制器包括第一队列和第二队列。 指令和索引在第一队列中排队，并且该第一排队包括将指令和与其相关联的索引转向相应的第一注册位置，同时保持指令和索引之间的关联。 相对于其中指令被接收到第一队列中的顺序，指令可以从第一队列中弹出。

公开(公告)号：US20090181010A1

公开(公告)日：2009-07-16

申请号：US12284723

申请日：2008-09-23

Applicant: Dan E. Berkowitz ,  Sungwoo Ryoo ,  Artin A. Shoukas ,  Gaurav Gupta ,  Lewis Romer

Inventor： Dan E. Berkowitz ,  Sungwoo Ryoo ,  Artin A. Shoukas ,  Gaurav Gupta ,  Lewis Romer

IPC: A61K39/395 ,  A61K31/7088 ,  A61K38/00 ,  C12Q1/34

CPC classification number: C12N15/1137 ,  A61K31/00 ,  C12N2310/11 ,  C12N2310/14 ,  C12Y305/03001

Abstract: The instant invention provides methods and compositions for the treatment of. atherosclerotic disease. Specifically, the invention provides methods and compositions for modulating the activity of Arginase II, the production of Arginase II or the amount of free Arginase II for the treatment of atherosclerotic disease.

Abstract translation: 本发明提供了用于治疗的方法和组合物。 动脉粥样硬化疾病 具体地，本发明提供了用于调节精氨酸酶II的活性，精氨酸酶II的产生或用于治疗动脉粥样硬化疾病的游离精氨酸酶II的量的方法和组合物。

公开(公告)号：US20070213732A1

公开(公告)日：2007-09-13

申请号：US11684764

申请日：2007-03-12

Applicant: A. Jay Khanna ,  Isador H. Lieberman ,  Karthikeyan Ponnusamy ,  Gaurav Gupta ,  Sravisht Iyer ,  Alexander Hui ,  Christopher Yu ,  Kartik Trehan

Inventor： A. Jay Khanna ,  Isador H. Lieberman ,  Karthikeyan Ponnusamy ,  Gaurav Gupta ,  Sravisht Iyer ,  Alexander Hui ,  Christopher Yu ,  Kartik Trehan

IPC: A61B17/58

CPC classification number: A61B17/8685 ,  A61B17/8625 ,  A61B17/864 ,  A61B17/8855

Abstract: An orthopedic screw system. The screw system comprises an outer member and an inner screw. The outer member has a longitudinal inner channel that defines an interior sidewall and is provided with screw threads on its exterior and interior sidewalls. An inner screw has threads constructed and arranged to engage with those on the interior sidewall, such that the inner screw may be secured within the inner channel. When secured within the inner channel, at least a portion of the length of the inner screw extends beyond the outer member. Methods of installing the orthopedic screw system into osteoporotic or otherwise weakened bone are also disclosed.

Abstract translation: 矫形螺钉系统。 螺杆系统包括外部构件和内部螺钉。 外部构件具有限定内侧壁的纵向内部通道，并且在其外部和内部侧壁上设置有螺纹。 内螺纹具有构造和布置成与内侧壁上的那些接合的螺纹，使得内螺钉可以固定在内通道内。 当固定在内部通道内时，内螺纹的长度的至少一部分延伸超出外部构件。 还公开了将矫形螺钉系统安装在骨质疏松或其它削弱的骨中的方法。

公开(公告)号：US20250049933A1

公开(公告)日：2025-02-13

申请号：US18922478

申请日：2024-10-22

Applicant: Misbahuddin Rafeeq ,  Gaurav Gupta

Inventor： Misbahuddin Rafeeq ,  Gaurav Gupta

IPC: A61K47/59 ,  A61K9/51 ,  A61P35/00

Abstract: The present invention provides a drug delivery system for targeted cancer treatment, comprising: a GEM-PLGA complex, wherein the complex contains 150 mg of GEM-PLGA, equivalent to 25 mg of gemcitabine (GEM); Acetone in an amount of 10 ml as a solvent for the GEM-PLGA complex; Polyvinyl alcohol (PVA) solution in an amount of 20 ml, with a concentration of 2% w/v, used as a stabilizer for the formulation; and a Layer-by-Layer nanoparticle (LbL-NP) formulation encapsulating the GEM-PLGA complex and configured to release GEM in a controlled manner upon administration. The physiochemical properties of Caps-GEM LbL NPs was evaluated such as particle size, zeta potential, percent entrapment efficiency (% EE), loading of drug and In-vitro drug release behavior. The surface morphology of LbL NP's was evaluated by scanning electronic microscopy (SEM).

公开(公告)号：US09569570B2

公开(公告)日：2017-02-14

申请号：US14675757

申请日：2015-04-01

Applicant: Gourav Kapoor ,  Gaurav Gupta ,  Syed Shakir Iqbal

Inventor： Gourav Kapoor ,  Gaurav Gupta ,  Syed Shakir Iqbal

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5072 ,  G06F17/5077

Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.

Abstract translation: 用于集成电路的可配置延迟单元包括CMOS反相器和第一至第四晶体管。 第三晶体管的漏极连接到第四晶体管的漏极，用于产生输出信号。 CMOS反相器的输出端子与第一晶体管的源极之间的连接，CMOS反相器的输出端子与第二晶体管的漏极之间的连接以及第一晶体管的源极和漏极之间的连接 第二晶体管是可配置的，使用电子设计自动化（EDA）工具来实现第一，第二，第三，第四和第五延迟值。 可以通过仅在集成电路的一个或多个金属层中进行改变来编程所得到的延迟值。