-
1.发明授权Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer 有权矢量传输系统用于将不连续的矢量元素打包在一起成为单个总线传输公开(公告)号：US07610469B2
公开(公告)日：2009-10-27
申请号：US10812323
申请日：2004-03-29
申请人： Ahmad R. Ansari
发明人： Ahmad R. Ansari
IPC分类号： G06F9/345
CPC分类号： G06F9/30043 , G06F9/30087 , G06F9/3455 , G06F9/383 , G06F9/3861
摘要： A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting. An address error exception occurs when the ending address of the vector data to be transferred is not within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined in parallel with determining the starting address of the vector data to be transferred.
摘要翻译： 用于处理计算机系统中的存储器和数据处理器之间的矢量数据传送的矢量传送单元。 向量数据传输指令被发布到向量传送单元中的指令队列。 用于执行突发传送的程序指令包括确定要传送的向量数据的起始地址，要传送的向量数据的结束地址以及要传送的向量数据的结束地址是否在同一虚拟存储器页内 作为起始地址。 要传送的矢量数据的结束地址基于要传送的数据元素的数量，要传送的矢量数据的步幅以及要传送的矢量数据元素的宽度来确定。 当要传送的数据量可以被二进制整数时，通过移位来执行数据元素的跨步和宽度的乘法。 要传送的向量数据的结束地址与起始地址不在同一虚拟内存页内时，会发生地址错误异常。 要确定要传送的矢量数据的起始地址并行确定要传送的矢量数据的结束地址。
-
公开(公告)号：US07590822B1
公开(公告)日：2009-09-15
申请号：US10912865
申请日：2004-08-06
IPC分类号： G06F15/00
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/3877 , G06F9/3897
摘要： Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.
摘要翻译： 描述了当协处理器可以更新其内部寄存器内容而不对处理器的负面影响时向协处理器指示的方法和装置。 控制器耦合在协处理器和处理器之间，其中控制器配置有状态机以通过处理器的流水线阶段跟踪指令。
-
公开(公告)号：US07546441B1
公开(公告)日：2009-06-09
申请号：US10912844
申请日：2004-08-06
IPC分类号： G06F9/00
CPC分类号： G06F9/3869 , G06F9/30181 , G06F9/3877 , G06F9/3897
摘要： A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.
摘要翻译： 描述处理器和协处理器之间的控制器接口。 控制器耦合到处理器以提供用于以第一频率操作的处理器接口，其中第一频率是处理器的操作频率。 控制器耦合到协处理器以提供用于在第二频率下操作的协处理器接口，其中第二频率是协处理器的操作频率，其慢于或等于第一频率。 控制器被配置为在第一频率和第二频率两者下操作，部分地在处理器和协处理器之间进行握手，使得处理器不必被放慢到第二频率以与协处理器一起操作。
-
公开(公告)号：US07406670B1
公开(公告)日：2008-07-29
申请号：US11888774
申请日：2007-08-01
CPC分类号： G06F11/27
摘要： Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.
摘要翻译： 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。
-
公开(公告)号：US07346759B1
公开(公告)日：2008-03-18
申请号：US10912897
申请日：2004-08-06
IPC分类号： G06F15/76
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/30145 , G06F9/30181 , G06F9/3867 , G06F9/3897
摘要： Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.
摘要翻译： 描述了用于处理器和协处理器的解码器接口的方法和装置。 输入指令寄存器存储来自处理器的输入指令。 配置指令寄存器存储指令。 耦合到输入指令寄存器和配置指令寄存器的比较/指针逻辑被配置为将来自处理器的输入指令与存储在配置寄存器中的指令进行比较，以确定是否存在匹配，并且被配置为提供与 具有与输入指令匹配的指令的指令的配置指令寄存器的配置指令寄存器，其中指针具有比输入指令少的位。
-
6.发明授权公开(公告)号：US07231621B1
公开(公告)日：2007-06-12
申请号：US10837395
申请日：2004-04-30
申请人： Nigel G. Herron , Ahmad R. Ansari , Stephen M. Douglass , Anthony Correale, Jr. , Leslie M. DeBruyne
发明人： Nigel G. Herron , Ahmad R. Ansari , Stephen M. Douglass , Anthony Correale, Jr. , Leslie M. DeBruyne
CPC分类号： G01R31/31718 , G01R31/31725 , G01R31/318519
摘要： Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.
摘要翻译： 用于生成具有嵌入式处理器的可编程逻辑器件的测试程序的方法和装置。 获得预定代码以锻炼所识别的至少一个速度限制路径。 对于预定代码，添加包装器代码以提供测试程序，包装器代码部分地用于将预定代码加载到嵌入式处理器的高速缓存中，用于测试所识别的嵌入式处理器的至少一个速度限制路径。
-
公开(公告)号：US06522167B1
公开(公告)日：2003-02-18
申请号：US09757760
申请日：2001-01-09
IPC分类号： G06F738
CPC分类号： G06F15/7867
摘要： A data processing system having a user configurable memory controller, one or more block RAMS, and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.
摘要翻译： 具有用户可配置存储器控制器，一个或多个块RAMS和处理器核的数据处理系统可以被配置在单个现场可编程门阵列（FPGA）中。 块RAM的地址深度和等待状态的数量可以由用户选择，并且可以在FPGA的配置之前设置，也可以使用处理器核心的指令进行编程。 还公开了可以优化地址深度和等待状态数以达到性能水平的算法。 本发明可以应用于具有单独的指令和数据侧的设计。
-
公开(公告)号：US08769231B1
公开(公告)日：2014-07-01
申请号：US12182934
申请日：2008-07-30
CPC分类号： G06F3/0659 , G06F13/16 , G06F13/4022
摘要： A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.
摘要翻译： 描述了一种用于处理器块ASIC核心的交叉开关装置和用于其先前读取模式的冲洗写入方法。 在读写模式下的操作用于与可编程逻辑结构相连的第一个处理器模块接口。 从使用可编程逻辑结构实例化的事务发起设备向第一处理器块接口发送至少一个写入命令。 至少一个写命令被发布在第一处理器块接口中。 接收到的至少一个写命令被存储在交叉开关装置的命令队列中。 由微处理器启动的读命令被发送到交叉开关装置。 所述至少一个写入命令具有与所述读取命令相对于目标目标的地址重叠。 读取命令在交叉开关装置中被暂时阻止，直到至少一个写命令的命令阶段完成。
-
公开(公告)号：US07958414B1
公开(公告)日：2011-06-07
申请号：US12888317
申请日：2010-09-22
申请人： Ahmad R. Ansari , Ting Lu , Ismed D. Hartanto
发明人： Ahmad R. Ansari , Ting Lu , Ismed D. Hartanto
CPC分类号： H03K19/17768 , G11C7/20
摘要： An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.
摘要翻译： 公开了增强内部存储器的安全性的方法的实施例。 对于该方法的该实施例，应用特定块在功能模式下操作，并且启动应用特定块的复位。 响应于启动的复位，内部自检引擎至少进行一次写入，其中至少一次写入在复位模式期间覆盖存储在内部存储器中的数据。
-
公开(公告)号：US07788470B1
公开(公告)日：2010-08-31
申请号：US12057353
申请日：2008-03-27
IPC分类号： G06F9/00
CPC分类号： G06F9/3855 , G06F9/3857 , G06F9/3877
摘要： A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.
摘要翻译： 描述了用于支持指令执行不正常的方法和控制器。 微处理器经由控制器耦合到协处理器。 微处理器和控制器接收到指令。 分别与指令相关联的指示由微处理器产生，并且指令从第一个队列弹出，以供协处理器执行。 控制器包括第一队列和第二队列。 指令和索引在第一队列中排队，并且该第一排队包括将指令和与其相关联的索引转向相应的第一注册位置，同时保持指令和索引之间的关联。 相对于其中指令被接收到第一队列中的顺序，指令可以从第一队列中弹出。
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.029 秒)
