Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes

Invention Grant

US07790622B2 Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes 有权

Title translation: 在CMOS半导体制造工艺中去除栅极侧壁间隔物的方法

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Patent Title: Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes
Patent Title (中): 在CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
Application No.: US11778038

Application Date: 2007-07-14
Publication No.: US07790622B2

Publication Date: 2010-09-07
Inventor: Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
Applicant: Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
Applicant Address: KR Suwon-Si US NY Armonk
Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
Current Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
Current Assignee Address: KR Suwon-Si US NY Armonk
Agency: F. Chau & Associates, LLC
Main IPC: H01L21/311
IPC: H01L21/311

Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes

Abstract:

Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract(Chinese):

提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

Public/Granted literature

US20090017625A1 Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes Public/Granted day:2009-01-15

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Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3105	......后处理
H01L21/311	.......绝缘层的刻蚀