Invention Grant
US07804129B2 Recessed gate electrode MOS transistor and method for fabricating the same
有权
嵌入式栅电极MOS晶体管及其制造方法
- Patent Title: Recessed gate electrode MOS transistor and method for fabricating the same
- Patent Title (中): 嵌入式栅电极MOS晶体管及其制造方法
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Application No.: US11157999Application Date: 2005-06-21
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Publication No.: US07804129B2Publication Date: 2010-09-28
- Inventor: Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
- Applicant: Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2005-0036051 20050429
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L21/3205

Abstract:
Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
Public/Granted literature
- US20060273381A1 Transistor and method for fabricating the same Public/Granted day:2006-12-07
Information query
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