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    Method for fabricating a semiconductor device with a FinFET
    3.
    发明授权
    Method for fabricating a semiconductor device with a FinFET 有权
    用FinFET制造半导体器件的方法

    公开(公告)号：US07915108B2

    公开(公告)日：2011-03-29

    申请号：US11646288

    申请日：2006-12-28

    Applicant: Se-Aug Jang ,  Hong-Seon Yang ,  Tae-Hang Ahn

    Inventor： Se-Aug Jang ,  Hong-Seon Yang ,  Tae-Hang Ahn

    IPC: H01L21/336 ,  H01L31/062

    CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10844 ,  H01L29/66795 ,  H01L29/7851

    Abstract: A method for fabricating a semiconductor device includes forming a device isolation structure in a substrate to define active regions, forming a hard mask pattern to open a region defining an active region pattern and to cover the device isolation structure, forming the active region pattern by selectively recessing the device isolation structure formed in the opened region using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulation layer over the substrate to cover at least the active region pattern, and forming a gate electrode over the gate insulation layer to cover at least the active region pattern.

    Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成器件隔离结构以限定有源区域，形成硬掩模图案以打开限定有源区域图案的区域并覆盖器件隔离结构，通过选择性地形成有源区域图案 使用硬掩模图案作为蚀刻阻挡层使形成在开放区域中的器件隔离结构凹陷，去除硬掩模图案，在衬底上方形成栅极绝缘层以至少覆盖有源区域图案，并在其上形成栅电极 栅极绝缘层以至少覆盖有源区域图案。

    METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE 有权
    用于在半导体器件中形成双绞线的方法

    公开(公告)号：US20110027988A1

    公开(公告)日：2011-02-03

    申请号：US12646478

    申请日：2009-12-23

    Applicant: Sun-Hwan HWANG ,  Se-Aug Jang ,  Kee-Joon Oh ,  Soon-Young Park

    Inventor： Sun-Hwan HWANG ,  Se-Aug Jang ,  Kee-Joon Oh ,  Soon-Young Park

    IPC: H01L21/283

    CPC classification number: H01L21/743 ,  H01L27/10876 ,  H01L27/10891

    Abstract: Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer.

    Abstract translation: 提供了一种在半导体器件中形成掩埋字线的方法。 该方法包括通过蚀刻衬垫层和衬底形成沟槽，形成导电层以填充沟槽，使导电层平坦化直到焊盘层露出，在平坦化导电层上执行回蚀刻工艺，并执行 在形成导电层中的至少一个，导电层的平坦化和在平坦化的导电层上执行回蚀处理之后，在氮化物基气体的气氛中进行退火处理。

    RECESSED GATE ELECTRODE MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    5.
    发明申请
    RECESSED GATE ELECTRODE MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
    闭合栅极电极MOS晶体管及其制造方法

    公开(公告)号：US20100323495A1

    公开(公告)日：2010-12-23

    申请号：US12861111

    申请日：2010-08-23

    Applicant: Jun Ki KIM ,  Soo Hyun KIM ,  Hyun Chul SOHN ,  Se Aug JANG

    Inventor： Jun Ki KIM ,  Soo Hyun KIM ,  Hyun Chul SOHN ,  Se Aug JANG

    IPC: H01L21/762 ,  H01L21/28

    CPC classification number: H01L29/66795 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7853

    Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

    Abstract translation: 公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。 该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层 去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域， 对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

    Recessed gate electrode MOS transistor and method for fabricating the same
    6.
    发明授权
    Recessed gate electrode MOS transistor and method for fabricating the same 有权
    嵌入式栅电极MOS晶体管及其制造方法

    公开(公告)号：US07804129B2

    公开(公告)日：2010-09-28

    申请号：US11157999

    申请日：2005-06-21

    Applicant: Jun Ki Kim ,  Soo Hyun Kim ,  Hyun Chul Sohn ,  Se Aug Jang

    Inventor： Jun Ki Kim ,  Soo Hyun Kim ,  Hyun Chul Sohn ,  Se Aug Jang

    IPC: H01L29/76 ,  H01L21/3205

    CPC classification number: H01L29/66795 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7853

    Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

    Abstract translation: 公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。 该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层 去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域， 对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

    Transistor structure of memory device and method for fabricating the same
    7.
    发明授权
    Transistor structure of memory device and method for fabricating the same 有权
    存储器件的晶体管结构及其制造方法

    公开(公告)号：US07601583B2

    公开(公告)日：2009-10-13

    申请号：US11962100

    申请日：2007-12-21

    Applicant: Se Aug Jang ,  Yong Soo Kim ,  Jae Geun Oh ,  Jae Sung Rohh ,  Hyun Chul Sohn

    Inventor： Se Aug Jang ,  Yong Soo Kim ,  Jae Geun Oh ,  Jae Sung Rohh ,  Hyun Chul Sohn

    IPC: H01L29/72

    CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

    Abstract translation: 存储器件包括从半导体衬底突出的有源区。 在活动区域​​中形成凹部。 在半导体衬底上形成场氧化物层。 栅极电极延伸穿过有源区域同时与凹部重叠。 栅极绝缘层介于栅电极和有源区之间。 源极和漏极区域形成在有源区域中。 如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。 晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

    TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME
    8.
    发明申请
    TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME 失效
    具有垂直通道的晶体管及其制造方法

    公开(公告)号：US20090218616A1

    公开(公告)日：2009-09-03

    申请号：US12165427

    申请日：2008-06-30

    Applicant: Se-Aug JANG ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Min-Gyu Sung ,  Tae-Yoon Kim ,  Sook-Joo Kim

    Inventor： Se-Aug JANG ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Min-Gyu Sung ,  Tae-Yoon Kim ,  Sook-Joo Kim

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66666 ,  H01L27/10808 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4966 ,  H01L29/7827

    Abstract: A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.

    Abstract translation: 提供了包括垂直沟道晶体管的半导体器件和用于形成晶体管的方法，其可以显着降低字线的电阻。 垂直沟道晶体管包括：衬底，其包括各自具有对应于沟道区的下部的柱。 在包括支柱的基板上形成栅极绝缘层。 使用具有低电阻的金属层来形成周围的栅电极以降低字线的电阻。 在栅绝缘层和周围栅电极之间形成阻挡金属层，从而防止绝缘层的特性劣化。 连接形成在阻挡层上的栅电极以围绕每个支柱的下部的世界线。

    Method for manufacturing recess gate in a semiconductor device
    9.
    发明授权
    Method for manufacturing recess gate in a semiconductor device 有权
    在半导体器件中制造凹槽的方法

    公开(公告)号：US07579265B2

    公开(公告)日：2009-08-25

    申请号：US11646282

    申请日：2006-12-28

    Applicant: Se-Aug Jang ,  Heung-Jae Cho ,  Tae-Yoon Kim

    Inventor： Se-Aug Jang ,  Heung-Jae Cho ,  Tae-Yoon Kim

    IPC: H01L21/00

    CPC classification number: H01L29/66553 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/66621

    Abstract: A method for manufacturing a recess gate in a semiconductor device includes forming a device isolation structure on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the active region through an etching process using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulating layer over the substrate, and forming a gate electrode over the gate insulating layer to cover at least the recess pattern.

    Abstract translation: 一种用于制造半导体器件中的凹槽的方法，包括在衬底上形成器件隔离结构以限定有源区，在衬底上形成硬掩模图案，以选择性地暴露有源区的至少一部分，形成凹陷图案 在有源区域中，通过使用硬掩模图案作为蚀刻阻挡层的蚀刻工艺，去除硬掩模图案，在衬底上形成栅极绝缘层，以及在栅极绝缘层上方形成栅电极以至少覆盖凹槽图案 。

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