发明授权
US07812634B1 Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together
有权
可编程逻辑器件收发器架构，便于将各种数量的收发器通道一起使用
- 专利标题： Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together
- 专利标题（中）： 可编程逻辑器件收发器架构，便于将各种数量的收发器通道一起使用
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申请号： US11726471申请日： 2007-03-21
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公开(公告)号： US07812634B1公开(公告)日： 2010-10-12
- 发明人: Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
- 申请人： Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Robert R. Jackson
- 主分类号： H03K19/173
- IPC分类号： H03K19/173
摘要：
Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.
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