Invention Grant
US07816962B2 Delay locked loop with improved jitter and clock delay compensating method thereof
有权
延迟锁定环路,具有改进的抖动和时钟延迟补偿方法
- Patent Title: Delay locked loop with improved jitter and clock delay compensating method thereof
- Patent Title (中): 延迟锁定环路,具有改进的抖动和时钟延迟补偿方法
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Application No.: US12284060Application Date: 2008-09-18
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Publication No.: US07816962B2Publication Date: 2010-10-19
- Inventor: Kyung-Hoon Kim
- Applicant: Kyung-Hoon Kim
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Priority: KR2003-52288 20030729
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.
Public/Granted literature
- US20090033392A1 Delay locked loop with improved jitter and clock delay compenstating method thereof Public/Granted day:2009-02-05
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