公开(公告)号：US08884862B2

公开(公告)日：2014-11-11

申请号：US12946176

申请日：2010-11-15

Applicant: Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

Inventor： Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

IPC: G09G3/36

CPC classification number: G09G3/3655 ,  G09G2300/0814 ,  G09G2310/0281 ,  G09G2320/0252 ,  G09G2330/021

Abstract: A display device includes: a plurality of pixels; a data driver connected to the plurality of pixels by a plurality of data lines and applying data signals to the plurality of pixels; a scan driver connected to the plurality of pixels by a plurality of scan lines and applying scan signals to the plurality of pixels for the data signals to be applied to the plurality of pixels; a boost driver connected to the plurality of pixels by a plurality of boost lines and applying boost signals, boosting the pixel voltage charged to the plurality of pixels by the data signals, to the plurality of pixels; and a boost voltage maintaining unit applying a restoring voltage restoring the voltage in the plurality of boost lines by the scan signal to the plurality of boost lines. The voltage generated in the boost line by the coupling may be quickly restored and the crosstalk may be minimized, thereby improving the image quality.

Abstract translation: 一种显示装置，包括：多个像素; 数据驱动器，其通过多条数据线连接到所述多个像素，并将数据信号施加到所述多个像素; 扫描驱动器，其通过多条扫描线连接到所述多个像素，并且将扫描信号施加到所述多个像素，以供应用于所述多个像素的数据信号; 升压驱动器，其通过多个升压线连接到所述多个像素，并且施加升压信号，通过所述数据信号将所述多个像素的像素电压升压到所述多个像素; 以及升压保持单元，通过所述扫描信号将多个升压线中的电压恢复到所述多个升压线路而施加恢复电压。 通过耦合在升压线中产生的电压可以快速恢复，并且串扰可以最小化，从而提高图像质量。

公开(公告)号：US08392741B2

公开(公告)日：2013-03-05

申请号：US12751671

申请日：2010-03-31

Applicant: Kyung-Hoon Kim ,  Kyung-Whan Kim

Inventor： Kyung-Hoon Kim ,  Kyung-Whan Kim

IPC: G06F1/04

CPC classification number: H03L7/06

Abstract: A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.

Abstract translation: 延迟控制电路包括：延迟单元，被配置为延迟与外部时钟和内部时钟之间的相位差对应的延迟的输入信号，并生成延迟的输入信号;延迟信息生成单元，被配置为基于 延迟信息和由包括等待时间控制电路的芯片引起的输入信号的延迟量;移位单元，被配置为与延迟信号相对应的延迟输入信号与内部时钟同步地移位;异步控制 单元，被配置为选择性地控制所述移位单元以输出所述延迟的输入信号，而不执行移位操作。

公开(公告)号：US08355288B2

公开(公告)日：2013-01-15

申请号：US13240136

申请日：2011-09-22

Applicant: Kyung-Hoon Kim ,  Patrick B. Moran

Inventor： Kyung-Hoon Kim ,  Patrick B. Moran

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4067

Abstract: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.

Abstract translation: 能够在不受噪声影响的情况下测量温度的半导体存储器件包括用于响应于控制信号感测当前温度的温度感测装置，其中半导体存储器件从激活时开始预定的时间进入省电模式 所述控制信号并且其中所述省电模式基本上没有功率消耗。 根据本发明的用于驱动半导体存储器件的方法包括响应于控制信号感测当前温度并且从控制信号的激活开始预定时间进入省电模式，其中省电模式具有 基本上没有功耗。

公开(公告)号：US20120098807A1

公开(公告)日：2012-04-26

申请号：US13278042

申请日：2011-10-20

Applicant: Seung-Kyu Lee ,  Dong-Hoon Lee ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Se-Hyang Kim

Inventor： Seung-Kyu Lee ,  Dong-Hoon Lee ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Se-Hyang Kim

IPC: G09G3/36 ,  G09G5/00 ,  H03K17/56

CPC classification number: G09G3/3655 ,  G09G3/3614 ,  G09G2300/0876 ,  H03K19/018507

Abstract: An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

Abstract translation: 公开了一种有源电平偏移（ALS）驱动电路和包括ALS驱动电路的液晶显示装置。 所述ALS驱动电路包括被配置为向第一节点施加第一极性电压并且向第二节点施加第二极性电压的输入单元，被配置为调整所述第一节点和所述第二节点的电压的电平补偿单元，以及 输出单元，被配置为根据第一和第二节点的调整的电压交替地输出第一电源电压和第二电源电压。

公开(公告)号：US20110211416A1

公开(公告)日：2011-09-01

申请号：US13105414

申请日：2011-05-11

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US07982517B2

公开(公告)日：2011-07-19

申请号：US12627415

申请日：2009-11-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03H11/26

CPC classification number: H03K5/131

Abstract: A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply.

Abstract translation: 延迟线包括延迟量调整单元，被配置为响应于第一延迟控制代码来调整输入信号的延迟量;以及延迟单元，被配置为确定具有第一变化宽度的延迟量的第一延迟块的数量 以及响应于第二延迟控制代码具有第二变化宽度的延迟量的多个第二延迟块，其中具有第一变化宽度的延迟量和具有第二变化宽度的延迟量由延迟量调整确定 单元，并且第一和第二变化宽度对应于电源的电平变化。

公开(公告)号：US07977968B2

公开(公告)日：2011-07-12

申请号：US12288882

申请日：2008-10-24

Applicant: Yong-Ki Kim ,  Kyung-Hoon Kim

Inventor： Yong-Ki Kim ,  Kyung-Hoon Kim

IPC: H03K17/16 ,  H03K19/003

CPC classification number: G11C7/1048 ,  G11C11/4093

Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

Abstract translation: 一种半导体存储器件，包括：用于基于从外部源输入的代码控制信号输出多个代码信号的代码通道; 用于解码芯片选择信号的终端电阻器解码器，芯片终端（ODT）控制信号和多个代码信号，并且基于解码的信号输出多个选择信号; 以及ODT块，用于为输出数据焊盘提供响应于所述多个选择信号而选择的终端电阻器的阻抗。

公开(公告)号：US07965582B2

公开(公告)日：2011-06-21

申请号：US12157287

申请日：2008-06-09

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract translation: 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US07880849B2

公开(公告)日：2011-02-01

申请号：US11865827

申请日：2007-10-02

Applicant: Chul-Ho Kim ,  Kook-Chul Moon ,  Pil-Mo Choi ,  Ho-Suk Maeng ,  Sang-Hoon Lee ,  Kyung-Hoon Kim ,  Keun-Woo Park

Inventor： Chul-Ho Kim ,  Kook-Chul Moon ,  Pil-Mo Choi ,  Ho-Suk Maeng ,  Sang-Hoon Lee ,  Kyung-Hoon Kim ,  Keun-Woo Park

IPC: G02F1/1343 ,  G02F1/136

CPC classification number: G02F1/134336 ,  G02F1/136213 ,  G02F2001/134345 ,  H01L27/12 ,  H01L27/124

Abstract: A display panel includes gate lines formed on a substrate, storage electrode lines formed on the substrate and being parallel to the gate lines, data lines insulated from the gate lines and crossing the gate lines, a plurality of thin film transistors (TFTs) connected with the gate lines and the data lines, and pixel electrodes having a first sub-electrode connected with a TFT and a second sub-electrode formed at a side opposite the first sub-electrode with respect to a gate line, wherein the TFT and a storage electrode line are disposed between the first and second sub-electrodes.

Abstract translation: 显示面板包括形成在基板上的栅极线，形成在基板上并与栅极线平行的存储电极线，与栅极线绝缘并与栅极线交叉的数据线，多个薄膜晶体管（TFT） 栅极线和数据线以及与TFT相连的第一子电极和与第一子电极相对于栅极线形成的第二子电极的像素电极，其中TFT和存储器 电极线设置在第一和第二子电极之间。

公开(公告)号：US07800423B2

公开(公告)日：2010-09-21

申请号：US12343753

申请日：2008-12-24

Applicant: Kyung-Hoon Kim ,  Bo-Kyeom Kim

Inventor： Kyung-Hoon Kim ,  Bo-Kyeom Kim

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K2005/00065

Abstract: A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.

Abstract translation: 占空比校正电路包括占空比传感器，用于通过感测速度控制信号控制占空比感测速度，并通过感测时钟的占空比来输出校正信号;以及占空比校正器，用于控制时钟的占空比 响应于校正信号。