发明授权
- 专利标题： Low power serial link bus architecture
- 专利标题（中）： 低功率串行总线架构
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申请号： US11428247申请日： 2006-06-30
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公开(公告)号： US07817068B2公开(公告)日： 2010-10-19
- 发明人: Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
- 申请人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwegman, Lundberg & Woessner, P.A.
- 主分类号： H03M5/00
- IPC分类号： H03M5/00
摘要：
Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
公开/授权文献
- US20080001793A1 LOW POWER SERIAL LINK BUS ARCHITECTURE 公开/授权日：2008-01-03
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