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发明授权
US07818642B2 Hierarchical test response compaction for a plurality of logic blocks 有权
多个逻辑块的分层测试响应压缩

Hierarchical test response compaction for a plurality of logic blocks
摘要：
In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.
摘要（中）：

在一个实施例中，本发明包括第一级矩阵，每个包括m个输入端和n个输出端，每个输出端和耦合到处理器核心的第一级矩阵，以及分别耦合到第一级矩阵之一的n个输出端的第二级矩阵， 的第二级矩阵具有n个输入端和p个输出端，并且第二级矩阵的p个输出端对应于来自多个处理器核的压缩输出。 描述和要求保护其他实施例。

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