Invention Grant
- Patent Title: Spacer patterned augmentation of tri-gate transistor gate length
- Patent Title (中): 三栅极晶体管栅极长度的间隔图案化扩充
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Application No.: US12006063Application Date: 2007-12-28
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Publication No.: US07820512B2Publication Date: 2010-10-26
- Inventor: Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
- Applicant: Ravi Pillarisetty , Suman Datta , Jack Kavalieros , Brian S. Doyle , Uday Shah
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Ryder, Lu, Mazzeo and Konieczny, LLC
- Agent Douglas J. Ryder
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/336 ; H01L21/311

Abstract:
In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
Public/Granted literature
- US20090168498A1 Spacer patterned augmentation of tri-gate transistor gate length Public/Granted day:2009-07-02
Information query
IPC分类: