发明授权
- 专利标题: Transmitter with multiple phase locked loops
- 专利标题(中): 具有多个锁相环的变送器
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申请号: US12229813申请日: 2008-08-27
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公开(公告)号: US07821343B1公开(公告)日: 2010-10-26
- 发明人: Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
- 申请人: Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Mauriel Kapouytian & Treffert LLP
- 代理商 Ararat Kapouytian
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.
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