公开(公告)号：US09444656B2

公开(公告)日：2016-09-13

申请号：US13289791

申请日：2011-11-04

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Sriram Narayan

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Sriram Narayan

IPC: H04L25/03

CPC classification number: H04L25/03038 ,  H04L25/03146 ,  H04L2025/03573

Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种用于数据链路的接收机电路。 接收机电路至少包括第一信号路径，第二信号路径和路径选择器电路。 第一信号路径包括第一均衡电路，第二信号路径包括第二均衡电路。 路径选择器电路被配置为选择第一和第二信号路径的一个信号路径。 还公开了其它实施例和特征。

公开(公告)号：US08750406B2

公开(公告)日：2014-06-10

申请号：US13363098

申请日：2012-01-31

Applicant: Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

Inventor： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

IPC: H04L25/34 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

Abstract: One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

公开(公告)号：US08610466B2

公开(公告)日：2013-12-17

申请号：US13540410

申请日：2012-07-02

Applicant: Weiqi Ding ,  Mingde Pan

Inventor： Weiqi Ding ,  Mingde Pan

IPC: H03K5/22

CPC classification number: H03K3/356139 ,  H03K5/08

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract translation: 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：US08451883B1

公开(公告)日：2013-05-28

申请号：US12630674

申请日：2009-12-03

Applicant: Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

Inventor： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

IPC: H04B3/46

CPC classification number: G01R31/3171 ,  H04L1/0061 ,  H04L1/203 ,  H04L1/205 ,  H04L1/248 ,  H04L7/033 ,  H04L7/0334 ,  H04L7/048

Abstract: Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.

Abstract translation: 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和装置。 例如，集成电路设备的一个实施例可能能够确定与均衡的串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路。 均衡器可以在串行输入信号上接收和执行均衡以产生均衡的串行输入信号，并且眼睛观察器电路可以确定与均衡的串行输入信号相关联的眼图的水平和垂直边界。

公开(公告)号：US08433958B2

公开(公告)日：2013-04-30

申请号：US12884923

申请日：2010-09-17

Applicant: Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

Inventor： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC: G06F11/00

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：US08127215B2

公开(公告)日：2012-02-28

申请号：US13151717

申请日：2011-06-02

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03M13/03

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US08111784B1

公开(公告)日：2012-02-07

申请号：US12082483

申请日：2008-04-11

Applicant: Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

Inventor： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

IPC: H04L25/06

CPC classification number: H04L25/063

Abstract: Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

Abstract translation: 用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。 对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。 然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。 这在眼部切片位置建立了眼睛的上限值。 然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

公开(公告)号：US07821343B1

公开(公告)日：2010-10-26

申请号：US12229813

申请日：2008-08-27

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

IPC: H03L7/00

CPC classification number: H03L7/23

Abstract: A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

Abstract translation: 描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。 在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。 此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出 或第二PLL的输出。 在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。 在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。 在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。 本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。 在宽范围模式下，需要较宽的频率范围。 另一方面，在低抖动模式中，需要低抖动。

公开(公告)号：US07812591B1

公开(公告)日：2010-10-12

申请号：US12029659

申请日：2008-02-12

Applicant: Mingde Pan ,  Juei-Chu Tu ,  Weiqi Ding

Inventor： Mingde Pan ,  Juei-Chu Tu ,  Weiqi Ding

IPC: G01R19/00

CPC classification number: G01R19/16566

Abstract: More accurate signal detection circuitry in serial interfaces, particularly on a programmable integrated circuit device, such as a PLD, includes a high-speed, high-resolution, high-bandwidth comparator, along with digital filtering, to reduce the effect of process, temperature or supply variations. The comparator is used to compare a direct input signal with a programmable reference voltage, and, in a preferred embodiment, can detect the signal level within 8 mV accuracy. The output of the comparator may then be digitally filtered. Preferably, both a high-pass digital filter and a low-pass analog filter may be used to eliminate glitches and low-frequency noise. Preferably, the digital filters are programmable to adjust the sensitivity to noise. The filtered output is then latched and output to indicate receipt or loss of signal. This signal detect circuitry can operate reliably at data rates as high as 7 Gbps.

Abstract translation: 串行接口中更准确的信号检测电路，特别是可编程集成电路器件（如PLD），包括高速，高分辨率，高带宽比较器以及数字滤波，以减少工艺，温度的影响 或供应变化。 比较器用于将直接输入信号与可编程参考电压进行比较，并且在优选实施例中，可以在8mV精度内检测信号电平。 然后可以对比较器的输出进行数字滤波。 优选地，可以使用高通数字滤波器和低通模拟滤波器来消除毛刺和低频噪声。 优选地，数字滤波器可编程以调节对噪声的灵敏度。 然后滤波后的输出被锁存并输出以指示信号的接收或丢失。 该信号检测电路可以以高达7Gbps的数据速率可靠地工作。

公开(公告)号：US20100079200A1

公开(公告)日：2010-04-01

申请号：US12241706

申请日：2008-09-30

Applicant: Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

Inventor： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC: G05F1/10 ,  H01L21/336

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract translation: 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。