A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.